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PIC12F609/615/617 PIC12HV609/615 Data Sheet
8-Pin, Flash-Based 8-Bit CMOS Microcontrollers
*8-bit, 8-pin Devices Protected by Microchip's Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending.
2010 Microchip Technology Inc. DS41302D
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
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Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS41302D-page 2
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
8-Pin Flash-Based, 8-Bit CMOS Microcontrollers
High-Performance RISC CPU:
* Only 35 Instructions to Learn: - All single-cycle instructions except branches * Operating Speed: - DC - 20 MHz oscillator/clock input - DC - 200 ns instruction cycle * Interrupt Capability * 8-Level Deep Hardware Stack * Direct, Indirect and Relative Addressing modes
Peripheral Features:
* Shunt Voltage Regulator (PIC12HV609/615 only): - 5 volt regulation - 4 mA to 50 mA shunt range * 5 I/O Pins and 1 Input Only * High Current Source/Sink for Direct LED Drive - Interrupt-on-pin change or pins - Individually programmable weak pull-ups * Analog Comparator module with: - One analog comparator - Programmable on-chip voltage reference (CVREF) module (% of VDD) - Comparator inputs and output externally accessible - Built-In Hysteresis (software selectable) * Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler * Enhanced Timer1: - 16-bit timer/counter with prescaler - External Timer1 Gate (count enable) - Option to use OSC1 and OSC2 in LP mode as Timer1 oscillator if INTOSC mode selected - Option to use system clock as Timer1 * In-Circuit Serial ProgrammingTM (ICSPTM) via Two Pins
Special Microcontroller Features:
* Precision Internal Oscillator: - Factory calibrated to 1%, typical - Software selectable frequency: 4 MHz or 8 MHz * Power-Saving Sleep mode * Voltage Range: - PIC12F609/615/617: 2.0V to 5.5V - PIC12HV609/615: 2.0V to user defined maximum (see note) * Industrial and Extended Temperature Range * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Brown-out Reset (BOR) * Watchdog Timer (WDT) with independent Oscillator for Reliable Operation * Multiplexed Master Clear with Pull-up/Input Pin * Programmable Code Protection * High Endurance Flash: - 100,000 write Flash endurance - Flash retention: > 40 years * Self Read/ Write Program Memory (PIC12F617 only)
PIC12F615/617/HV615 ONLY:
* Enhanced Capture, Compare, PWM module: - 16-bit Capture, max. resolution 12.5 ns - Compare, max. resolution 200 ns - 10-bit PWM with 1 or 2 output channels, 1 output channel programmable "dead time," max. frequency 20 kHz, auto-shutdown * A/D Converter: - 10-bit resolution and 4 channels, samples internal voltage references * Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler
Low-Power Features:
* Standby Current: - 50 nA @ 2.0V, typical * Operating Current: - 11 A @ 32 kHz, 2.0V, typical - 260 A @ 4 MHz, 2.0V, typical * Watchdog Timer Current: - 1 A @ 2.0V, typical Note: Voltage across the shunt regulator should not exceed 5V.
2010 Microchip Technology Inc.
DS41302D-page 3
PIC12F609/615/617/12HV609/615
Program Memory Flash (words) 1024 1024 1024 1024 2048 Data Memory SRAM (bytes) 64 64 64 64 128
Device
Self Read/ Self Write
I/O
10-bit A/D Comparators ECCP (ch) 0 0 4 4 4 1 1 1 1 1
Timers 8/16-bit 1/1 1/1 2/1 2/1 2/1
Voltage Range
PIC12F609 PIC12HV609 PIC12F615 PIC12HV615 PIC12F617
-- -- -- --
YES
5 5 5 5 5
-- --
YES YES YES
2.0V-5.5V 2.0V-user defined 2.0V-5.5V 2.0V-user defined 2.0V-5.5V
8-Pin Diagram, PIC12F609/HV609 (PDIP, SOIC, MSOP, DFN)
VDD GP5/T1CKI/OSC1/CLKIN GP4/CIN1-/T1G/OSC2/CLKOUT GP3/MCLR/VPP
1 2 3 4
8 PIC12F609/ 7 HV609 6 5
VSS GP0/CIN+/ICSPDAT GP1/CIN0-/ICSPCLK GP2/T0CKI/INT/COUT
TABLE 1:
I/O GP0 GP1 GP2 GP3
(1)
PIC12F609/HV609 PIN SUMMARY (PDIP, SOIC, MSOP, DFN)
Pin 7 6 5 4 3 2 1 8 Comparators CIN+ CIN0COUT -- CIN1-- -- -- Timer -- -- T0CKI -- T1G T1CKI -- -- Interrupts IOC IOC INT/IOC IOC IOC IOC -- -- Pull-ups Y Y Y Y(2) Y Y -- -- Basic ICSPDAT ICSPCLK -- MCLR/VPP OSC2/CLKOUT OSC1/CLKIN VDD VSS
GP4 GP5 -- -- Note 1: 2:
Input only. Only when pin is configured for external MCLR.
DS41302D-page 4
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
8-Pin Diagram, PIC12F615/617/HV615 (PDIP, SOIC, MSOP, DFN)
VDD GP5/T1CKI/P1A*/OSC1/CLKIN GP4/AN3/CIN1-/T1G/P1B*/OSC2/CLKOUT GP3/T1G*/MCLR/VPP
1 2 3 4
8 PIC12F615/ 7 617/HV615 6 5
VSS GP0/AN0/CIN+/P1B/ICSPDAT GP1/AN1/CIN0-/VREF/ICSPCLK GP2/AN2/T0CKI/INT/COUT/CCP1/P1A
*
Alternate pin function.
TABLE 2:
I/O GP0 GP1 GP2 GP3 GP4 GP5 -- -- * Note 1: 2:
(1)
PIC12F615/617/HV615 PIN SUMMARY (PDIP, SOIC, MSOP, DFN)
Analog AN0 AN1 AN2 -- AN3 -- -- -- Comparator s CIN+ CIN0COUT -- CIN1-- -- -- Timer -- -- T0CKI T1G* T1G T1CKI -- -- CCP P1B -- CCP1/P1A -- P1B* P1A* -- -- Interrupts IOC IOC INT/IOC IOC IOC IOC -- -- Pull-ups Y Y Y Y(2) Y Y -- -- Basic ICSPDAT ICSPCLK/VREF -- MCLR/VPP OSC2/CLKOUT OSC1/CLKIN VDD VSS
Pin 7 6 5 4 3 2 1 8
Alternate pin function. Input only. Only when pin is configured for external MCLR.
2010 Microchip Technology Inc.
DS41302D-page 5
PIC12F609/615/617/12HV609/615
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 7 2.0 Memory Organization ................................................................................................................................................................ 11 3.0 Flash Program Memory Self Read/Self Write Control (PIC12F617 only).................................................................................. 27 4.0 Oscillator Module ....................................................................................................................................................................... 37 5.0 I/O Port ...................................................................................................................................................................................... 43 6.0 Timer0 Module .......................................................................................................................................................................... 53 7.0 Timer1 Module with Gate Control .............................................................................................................................................. 57 8.0 Timer2 Module (PIC12F615/617/HV615 only) .......................................................................................................................... 65 9.0 Comparator Module ................................................................................................................................................................... 67 10.0 Analog-to-Digital Converter (ADC) Module (PIC12F615/617/HV615 only) ............................................................................... 79 11.0 Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only) ............... 89 12.0 Special Features of the CPU ................................................................................................................................................... 107 13.0 Voltage Regulator .................................................................................................................................................................... 127 14.0 Instruction Set Summary ........................................................................................................................................................ 129 15.0 Development Support ............................................................................................................................................................. 139 16.0 Electrical Specifications ........................................................................................................................................................... 143 17.0 DC and AC Characteristics Graphs and Tables ...................................................................................................................... 171 18.0 Packaging Information ............................................................................................................................................................ 195 Appendix A: Data Sheet Revision History ......................................................................................................................................... 203 Appendix B: Migrating from other PIC(R) Devices ............................................................................................................................... 203 Index ................................................................................................................................................................................................. 205 The Microchip Web Site .................................................................................................................................................................... 209 Customer Change Notification Service ............................................................................................................................................. 209 Customer Support ............................................................................................................................................................................. 209 Reader Response ............................................................................................................................................................................. 210 Product Identification System ............................................................................................................................................................ 211 Worldwide Sales and Service ........................................................................................................................................................... 212
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DS41302D-page 6
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
1.0 DEVICE OVERVIEW
Block Diagrams and pinout descriptions of the devices are as follows: * PIC12F609/HV609 (Figure 1-1, Table 1-1) * PIC12F615/617/HV615 (Figure 1-2, Table 1-2) The PIC12F609/615/617/12HV609/615 devices are covered by this data sheet. They are available in 8-pin PDIP, SOIC, MSOP and DFN packages.
FIGURE 1-1:
PIC12F609/HV609 BLOCK DIAGRAM
INT Configuration 13 Program Counter Flash 1K X 14 Program Memory Data Bus 8 GPIO
8-Level Stack (13-Bit)
RAM 64 Bytes File Registers RAM Addr 9 Addr MUX
Program Bus
GP0 GP1 GP2 GP3 GP4 GP5
14 Instruction Reg Direct Addr 7
8
Indirect Addr
FSR Reg STATUS Reg 8
Power-up Timer Instruction Decode & Control OSC1/CLKIN OSC2/CLKOUT Internal Oscillator Block T1G T1CKI Timer0 T0CKI Timer1 MCLR VDD VSS Timing Generation Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8
3
MUX
ALU
W Reg
Shunt Regulator (PIC12HV609 only)
Comparator Voltage Reference Absolute Voltage Reference
Analog Comparator and Reference
CIN+ CIN0CIN1COUT
2010 Microchip Technology Inc.
DS41302D-page 7
PIC12F609/615/617/12HV609/615
FIGURE 1-2: PIC12F615/617/HV615 BLOCK DIAGRAM
INT Configuration 13 Flash 1K X 14 and 2K X 14** Program Memory Program Bus Program Counter Data Bus 8 GPIO
8-Level Stack (13-Bit)
RAM 64 Bytes and 128 Bytes** File Registers RAM Addr 9 Addr MUX
GP0 GP1 GP2 GP3 GP4 GP5
14 Instruction Reg Direct Addr 7
8
Indirect Addr
FSR Reg STATUS Reg 8
Power-up Timer Instruction Decode & Control OSC1/CLKIN OSC2/CLKOUT Internal Oscillator Block MCLR VDD VSS Timing Generation Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8
3
MUX
ALU
W Reg
T1G* T1G T1CKI
Shunt Regulator (PIC12HV615 only)
Timer0 T0CKI
Timer1
Timer2
Comparator Voltage Reference Analog-To-Digital Converter Absolute Voltage Reference
Analog Comparator and Reference
ECCP
AN0 AN1 AN2 AN3
CIN+ CIN0CIN1COUT
CCP1/P1A P1B P1A* P1B*
DS41302D-page 8
VREF * **
Alternate pin function. For the PIC12F617 only.
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 1-1:
Name GP0/CIN+/ICSPDAT
PIC12F609/HV609 PINOUT DESCRIPTION
Function GP0 CIN+ ICSPDAT Input Type TTL AN ST TTL AN ST ST ST ST -- TTL ST HV TTL AN ST -- -- TTL ST XTAL ST Power Power Output Type CMOS -- CMOS CMOS -- -- CMOS -- -- CMOS -- -- -- CMOS -- -- XTAL CMOS CMOS -- -- -- -- -- Description General purpose I/O with prog. pull-up and interrupt-on-change Comparator non-inverting input Serial Programming Data I/O General purpose I/O with prog. pull-up and interrupt-on-change Comparator inverting input Serial Programming Clock General purpose I/O with prog. pull-up and interrupt-on-change Timer0 clock input External Interrupt Comparator output General purpose input with interrupt-on-change Master Clear w/internal pull-up Programming voltage General purpose I/O with prog. pull-up and interrupt-on-change Comparator inverting input Timer1 gate (count enable) Crystal/Resonator FOSC/4 output General purpose I/O with prog. pull-up and interrupt-on-change Timer1 clock input Crystal/Resonator External clock input/RC oscillator connection Positive supply Ground reference HV= High Voltage XTAL=Crystal
GP1/CIN0-/ICSPCLK
GP1 CIN0ICSPCLK
GP2/T0CKI/INT/COUT
GP2 T0CKI INT COUT
GP3/MCLR/VPP
GP3 MCLR VPP
GP4/CIN1-/T1G/OSC2/ CLKOUT
GP4 CIN1T1G OSC2 CLKOUT
GP5/T1CKI/OSC1/CLKIN
GP5 T1CKI OSC1 CLKIN
VDD VSS
VDD VSS
Legend: AN=Analog input or output ST=Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output TTL = TTL compatible input
2010 Microchip Technology Inc.
DS41302D-page 9
PIC12F609/615/617/12HV609/615
TABLE 1-2: PIC12F615/617/HV615 PINOUT DESCRIPTION
Name GP0/AN0/CIN+/P1B/ICSPDAT Function GP0 AN0 CIN+ P1B ICSPDAT GP1/AN1/CIN0-/VREF/ICSPCLK GP1 AN1 CIN0VREF ICSPCLK GP2/AN2/T0CKI/INT/COUT/CCP1/ P1A GP2 AN2 T0CKI INT COUT CCP1 P1A GP3/T1G*/MCLR/VPP GP3 T1G* MCLR VPP GP4/AN3/CIN1-/T1G/P1B*/OSC2/ CLKOUT GP4 AN3 CIN1T1G P1B* OSC2 CLKOUT GP5/T1CKI/P1A*/OSC1/CLKIN GP5 T1CKI P1A* OSC1 CLKIN VDD VSS * Legend: VDD VSS Input Type TTL AN AN -- ST TTL AN AN AN ST ST AN ST ST -- ST -- TTL ST ST HV TTL AN AN ST -- -- -- TTL ST -- XTAL ST Power Power Output Type CMOS -- -- CMOS CMOS CMOS -- -- -- -- CMOS -- -- -- CMOS CMOS CMOS -- -- -- -- CMOS -- -- -- CMOS XTAL CMOS CMOS -- CMOS -- -- -- -- Description General purpose I/O with prog. pull-up and interrupt-onchange A/D Channel 0 input Comparator non-inverting input PWM output Serial Programming Data I/O General purpose I/O with prog. pull-up and interrupt-onchange A/D Channel 1 input Comparator inverting input External Voltage Reference for A/D Serial Programming Clock General purpose I/O with prog. pull-up and interrupt-onchange A/D Channel 2 input Timer0 clock input External Interrupt Comparator output Capture input/Compare input/PWM output PWM output General purpose input with interrupt-on-change Timer1 gate (count enable), alternate pin Master Clear w/internal pull-up Programming voltage General purpose I/O with prog. pull-up and interrupt-onchange A/D Channel 3 input Comparator inverting input Timer1 gate (count enable) PWM output, alternate pin Crystal/Resonator FOSC/4 output General purpose I/O with prog. pull-up and interrupt-onchange Timer1 clock input PWM output, alternate pin Crystal/Resonator External clock input/RC oscillator connection Positive supply Ground reference HV= High Voltage XTAL=Crystal
Alternate pin function. AN=Analog input or output ST=Schmitt Trigger input with CMOS levels
CMOS=CMOS compatible input or output TTL = TTL compatible input
DS41302D-page 10
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
2.0
2.1
MEMORY ORGANIZATION
Program Memory Organization
FIGURE 2-2:
PROGRAM MEMORY MAP AND STACK FOR THE PIC12F617
PC<12:0>
The PIC12F609/615/617/12HV609/615 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h03FFh) for the PIC12F609/615/12HV609/615 is physically implemented. For the PIC12F617, the first 2K x 14 (0000h-07FFh) is physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first 1K x 14 space for PIC12F609/615/12HV609/615 devices, and within the first 2K x 14 space for the PIC12F617 device. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).
CALL, RETURN RETFIE, RETLW
13
Stack Level 1 Stack Level 2
Stack Level 8 Reset Vector
0000h
FIGURE 2-1:
PROGRAM MEMORY MAP AND STACK FOR THE PIC12F609/615/12HV609/615
PC<12:0>
Interrupt Vector On-Chip Program Memory Page 0 Wraps to 0000h-07FFh
0004h 0005h 07FFh 0800h 1FFFh
CALL, RETURN RETFIE, RETLW
13
Stack Level 1 Stack Level 2
2.2
Data Memory Organization
Stack Level 8 Reset Vector
0000h
Interrupt Vector
0004h 0005h
On-chip Program Memory 03FFh 0400h
The data memory (see Figure 2-3) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 40h-7Fh in Bank 0 are General Purpose Registers, implemented as static RAM. For the PIC12F617, the register locations 20h-7Fh in Bank 0 and A0h-EFh in Bank 1 are general purpose registers implemented as Static RAM. Register locations F0h-FFh in Bank 1 point to addresses 70h-7Fh in Bank 0. All other RAM is unimplemented and returns `0' when read. The RP0 bit of the STATUS register is the bank select bit. RP0 0 Bank 0 is selected Bank 1 is selected 1
Wraps to 0000h-03FFh
1FFFh
Note:
The IRP and RP1 bits of the STATUS register are reserved and should always be maintained as `0's.
2010 Microchip Technology Inc.
DS41302D-page 11
PIC12F609/615/617/12HV609/615
2.2.1 GENERAL PURPOSE REGISTER FILE FIGURE 2-3: DATA MEMORY MAP OF THE PIC12F609/HV609
File Address Indirect Addr.(1) TMR0 PCL STATUS FSR GPIO 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h PCLATH INTCON PIR1 TMR1L TMR1H T1CON 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h VRCON CMCON0 CMCON1 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h ANSEL WPU IOC OSCTUNE PCON PCLATH INTCON PIE1 Indirect Addr.(1) OPTION_REG PCL STATUS FSR TRISIO File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
The register file is organized as 64 x 8 in the PIC12F609/615/12HV609/615, and as 128 x 8 in the PIC12F617. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 "Indirect Addressing, INDF and FSR Registers").
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1). These registers are static RAM. The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the "core" are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
3Fh General Purpose Registers 64 Bytes Accesses 70h-7Fh Bank 0 40h
6Fh 70h 7Fh
Accesses 70h-7Fh Bank 1
EFh F0h FFh
Unimplemented data memory locations, read as `0'. Note 1: Not a physical register.
DS41302D-page 12
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 2-4: DATA MEMORY MAP OF THE PIC12F615/617/HV615
File Address Indirect Addr.(1) TMR0 PCL STATUS FSR GPIO 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON CCPR1L CCPR1H CCP1CON PWM1CON ECCPAS VRCON CMCON0 CMCON1 ADRESH ADCON0 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h General Purpose Registers 96 Bytes from 20h-7Fh(2) Unimplemented for PIC12F615/HV615 3Fh General Purpose Registers 64 Bytes Accesses 70h-7Fh Bank 0 40h General Purpose Registers 32 Bytes(2) Unimplemented for PIC12F615/HV615
BFh
File Address Indirect Addr.(1) OPTION_REG PCL STATUS FSR TRISIO 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h PCLATH INTCON PIE1 PCON OSCTUNE PR2 APFCON WPU IOC PMCON1 PMCON2 PMADRL PMDATL
(2) (2)
8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h
(2) (2)
PMADRH PMDATH ANSEL
(2) (2)
ADRESL
C0h
6Fh 70h 7Fh
Accesses 70h-7Fh Bank 1
EFh F0h FFh
Unimplemented data memory locations, read as `0'. Note 1: 2: Not a physical register. Used for the PIC12F617 only.
2010 Microchip Technology Inc.
DS41302D-page 13
PIC12F609/615/617/12HV609/615
TABLE 2-1:
Addr Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Legend: 1: 2: INDF TMR0 PCL STATUS FSR GPIO -- -- -- -- PCLATH INTCON PIR1 -- TMR1L TMR1H T1CON -- -- -- -- -- -- -- -- VRCON CMCON0 -- CMCON1 -- -- -- -- Unimplemented Unimplemented Unimplemented -- -- T1ACS Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module's Register Program Counter's (PC) Least Significant Byte IRP(1) RP1(1) RP0 TO PD Z DC C xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx GP4 GP3 GP2 GP1 GP0 --x0 x000 -- -- -- -- -- PEIE -- -- T0IE -- Write Buffer for upper 5 bits of Program Counter INTE -- GPIE CMIF T0IF -- INTF -- GPIF TMR1IF ---0 0000 0000 0000 ---- 0--0 -- xxxx xxxx xxxx xxxx TMR1CS TMR1ON 0000 0000 -- -- -- -- -- -- -- -- -- COUT VRR CMOE FVREN CMPOL VR3 -- -- CMHYS -- VR2 CMR VR1 -- -- T1GSS CMSYNC VR0 CMCH 0-00 0000 0000 -0-0 -- ---0 0-10 -- -- -- 25, 115 53, 115 25, 115 18, 115 25, 115 43, 115 -- -- -- -- 25, 115 20, 115 22, 115 -- 57, 115 57, 115 62, 115 -- -- -- -- -- -- -- -- 76, 116 72, 116 -- 73, 116 -- -- -- Name
PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page
Indirect Data Memory Address Pointer -- Unimplemented Unimplemented Unimplemented Unimplemented -- GIE -- Unimplemented Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC -- GP5
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented CMVREN CMON
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented IRP and RP1 bits are reserved, always maintain these bits clear. Read only register.
DS41302D-page 14
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 2-2:
Addr Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh INDF TMR0 PCL STATUS FSR GPIO -- -- -- -- PCLATH INTCON PIR1 -- TMR1L TMR1H T1CON TMR2(3) T2CON(3) CCPR1L(3) CCPR1H(3) CCP1CON(3) PWM1CON(3) ECCPAS(3) -- VRCON CMCON0 -- CMCON1 -- ADRESH(2, 3) ADCON0(3) -- Unimplemented Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result ADFM VCFG -- CHS2 CHS1 CHS0 GO/DONE ADON -- -- T1ACS Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module's Register Program Counter's (PC) Least Significant Byte IRP(1) RP1(1) RP0 TO PD Z DC C xxxx xxxx 25, 116 xxxx xxxx 53, 116 0000 0000 25, 116 0001 1xxx 18, 116 xxxx xxxx 25, 116 GP4 GP3 GP2 GP1 GP0 --x0 x000 43, 116 -- -- -- -- -- PEIE ADIF -- T0IE CCP1IF Write Buffer for upper 5 bits of Program Counter INTE -- GPIE CMIF T0IF -- INTF TMR2IF GPIF TMR1IF -- -- -- -- Name
PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page
Indirect Data Memory Address Pointer -- Unimplemented Unimplemented Unimplemented Unimplemented -- GIE -- Unimplemented Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -- GP5
---0 0000 25, 116 0000 0000 20, 116 -00- 0-00 22, 116 -- --
xxxx xxxx 57, 116 xxxx xxxx 57, 116 0000 0000 62, 116 0000 0000 65, 116
Timer2 Module Register -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
-000 0000 66, 116 XXXX XXXX 90, 116 XXXX XXXX 90, 116
Capture/Compare/PWM Register 1 Low Byte Capture/Compare/PWM Register 1 High Byte P1M PRSEN ECCPASE -- PDC6 ECCPAS2 DC1B1 PDC5 ECCPAS1 DC1B0 PDC4 ECCPAS0 CCP1M3 PDC3 PSSAC1 CCP1M2 PDC2 PSSAC0 CCP1M1 PDC1 PSSBD1 CCP1M0 PDC0 PSSBD0
0-00 0000 89, 116 0000 0000 0000 0000 -- 105, 116 102, 116 --
Unimplemented CMVREN CMON -- COUT VRR CMOE FVREN CMPOL VR3 -- -- CMHYS -- VR2 CMR VR1 -- -- T1GSS CMSYNC VR0 CMCH
0-00 0000 76, 116 0000 -0-0 72, 116 -- --
---0 0-10 73, 116 -- --
xxxx xxxx 85, 116 00-0 0000 84, 116
Legend: Note 1: 2: 3:
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented IRP and RP1 bits are reserved, always maintain these bits clear. Read only register. PIC12F615/617/HV615 only.
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TABLE 2-3:
Addr Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh INDF OPTION_RE G PCL STATUS FSR TRISIO -- -- -- -- PCLATH INTCON PIE1 -- PCON -- OSCTUNE -- -- -- -- WPU(2) IOC -- -- -- -- -- -- -- -- ANSEL Addressing this location uses contents of FSR to address data memory (not a physical register) GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 xxxx xxxx 25, 116 1111 1111 19, 116 0000 0000 25, 116 PD TRISIO3(4) Z DC C 0001 1xxx 18, 116 xxxx xxxx 25, 116 TRISIO4 TRISIO2 TRISIO1 TRISIO0 --11 1111 44, 116 -- -- -- -- -- PEIE -- -- T0IE -- Write Buffer for upper 5 bits of Program Counter INTE -- GPIE CMIE T0IF -- INTF -- GPIF(3) TMR1IE -- -- -- -- Name
PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page
Program Counter's (PC) Least Significant Byte IRP(1) RP1(1) RP0 TO
Indirect Data Memory Address Pointer -- Unimplemented Unimplemented Unimplemented Unimplemented -- GIE -- Unimplemented -- Unimplemented -- Unimplemented Unimplemented Unimplemented Unimplemented -- -- Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- -- -- -- ANS3 -- ANS1 ANS0 -- -- WPU5 IOC5 WPU4 IOC4 -- IOC3 WPU2 IOC2 WPU1 IOC1 WPU0 IOC0 -- -- TUN4 TUN3 TUN2 TUN1 TUN0 -- -- -- -- -- POR BOR -- TRISIO5
---0 0000 25, 116 0000 0000 20, 116 ---- 0--0 21, 116 -- --
---- --qq 23, 116 -- --
---0 0000 41, 116 -- -- -- -- -- -- -- --
--11 -111 46, 116 --00 0000 46, 116 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
---- 1-11 45, 117
Legend: Note 1: 2: 3: 4:
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented IRP and RP1 bits are reserved, always maintain these bits clear. GP3 pull-up is enabled when MCLRE is `1' in the Configuration Word register. MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch exists. TRISIO3 always reads as `1' since it is an input only pin.
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TABLE 2-4:
Addr Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh PR2 APFCON -- WPU(2) IOC -- PMCON1(7) PMCON2(7) PMADRL(7) PMADRH(7) PMDATL(7) PMDATH(7) ADRESL(5, 6) ANSEL INDF OPTION_REG PCL STATUS FSR TRISIO -- -- -- -- PCLATH INTCON PIE1 -- PCON -- OSCTUNE -- Addressing this location uses contents of FSR to address data memory (not a physical register) GPPU IRP(1) INTEDG RP1(1) T0CS T0SE PSA PS2 PS1 PS0 xxxx xxxx 25, 116 1111 1111 19, 116 0000 0000 25, 116 PD TRISIO3(4) Z DC C 0001 1xxx 18, 116 xxxx xxxx 25, 116 TRISIO4 TRISIO2 TRISIO1 TRISIO0 --11 1111 44, 116 -- -- -- -- -- PEIE ADIE -- T0IE CCP1IE Write Buffer for upper 5 bits of Program Counter INTE -- GPIE CMIE T0IF -- INTF TMR2IE GPIF(3) TMR1IE -- -- -- -- Name
PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page
Program Counter's (PC) Least Significant Byte RP0 TO
Indirect Data Memory Address Pointer -- Unimplemented Unimplemented Unimplemented Unimplemented -- GIE -- -- TRISIO5
---0 0000 25, 116 0000 0000 20, 116 -00- 0-00 21, 116 -- --
Unimplemented -- Unimplemented -- Unimplemented Timer2 Module Period Register -- Unimplemented -- -- Unimplemented -- -- -- -- -- WREN WR RD -- -- WPU5 IOC5 WPU4 IOC4 -- IOC3 WPU2 IOC2 WPU1 IOC1 WPU0 IOC0 -- -- T1GSEL -- -- P1BSEL P1ASEL -- -- TUN4 TUN3 TUN2 TUN1 TUN0 -- -- -- -- -- POR BOR
---- --qq 23, 116 -- --
---0 0000 41, 116 -- --
1111 1111 65, 116 ---0 --00 21, 116 -- --
--11 -111 46, 116 --00 0000 46, 116 -- ---- -000 ---- ----- 29 -- 28 28 28 28
Program Memory Control Register 2 (not a physical register). PMADRL7 PMADRL6 PMADRL5 PMADRL4 -- PMDATL7 -- -- PMDATL6 -- -- PMDATL5 -- PMDATL4 PMADRL3 -- PMDATL3 PMADRL2 PMADRL1
PMADRL0 0000 0000
PMADRH2 PMADRH1 PMADRH0 ---- -000 PMDATL2 PMDATL1 PMDATL0 0000 0000 --00 0000
Program Memory Data Register High Byte.
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result -- ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0
xxxx xxxx 85, 117 -000 1111 45, 117
Legend: Note 1: 2: 3: 4: 5: 6: 7:
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented IRP and RP1 bits are reserved, always maintain these bits clear. GP3 pull-up is enabled when MCLRE is `1' in the Configuration Word register. MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch exists. TRISIO3 always reads as `1' since it is an input only pin. Read only register. PIC12F615/617/HV615 only. PIC12F617 only.
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2.2.2.1 STATUS Register
The STATUS register, shown in Register 2-1, contains: * the arithmetic status of the ALU * the Reset status * the bank select bits for data memory (RAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as `000u u1uu' (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits, see the Section 14.0 "Instruction Set Summary". Note 1: Bits IRP and RP1 of the STATUS register are not used by the PIC12F609/615/617/ 12HV609/615 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products. 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 2-1:
Reserved IRP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 bit 5
STATUS: STATUS REGISTER
Reserved RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IRP: This bit is reserved and should be maintained as `0' RP1: This bit is reserved and should be maintained as `0' RP0: Register Bank Select bit (used for direct addressing) 1 = Bank 1 (80h - FFh) 0 = Bank 0 (00h - 7Fh) TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow, the polarity is reversed. 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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2.2.2.2 OPTION Register
Note: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit to `1' of the OPTION register. See Section 6.1.3 "Software Programmable Prescaler". The OPTION register is a readable and writable register, which contains various control bits to configure: * * * * Timer0/WDT prescaler External GP2/INT interrupt Timer0 Weak pull-ups on GPIO
REGISTER 2-2:
R/W-1 GPPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7
OPTION_REG: OPTION REGISTER
R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual PORT latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of GP2/INT pin 0 = Interrupt on falling edge of GP2/INT pin T0CS: Timer0 Clock Source Select bit 1 = Transition on GP2/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on GP2/T0CKI pin 0 = Increment on low-to-high transition on GP2/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits
BIT VALUE 000 001 010 011 100 101 110 111 TIMER0 RATE WDT RATE 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
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2.2.2.3 INTCON Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, GPIO change and external GP2/INT pin interrupts.
REGISTER 2-3:
R/W-0 GIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7
INTCON: INTERRUPT CONTROL REGISTER
R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 GPIE R/W-0 T0IF R/W-0 INTF R/W-0 GPIF bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt INTE: GP2/INT External Interrupt Enable bit 1 = Enables the GP2/INT external interrupt 0 = Disables the GP2/INT external interrupt GPIE: GPIO Change Interrupt Enable bit(1) 1 = Enables the GPIO change interrupt 0 = Disables the GPIO change interrupt T0IF: Timer0 Overflow Interrupt Flag bit(2) 1 = Timer0 register has overflowed (must be cleared in software) 0 = Timer0 register did not overflow INTF: GP2/INT External Interrupt Flag bit 1 = The GP2/INT external interrupt occurred (must be cleared in software) 0 = The GP2/INT external interrupt did not occur GPIF: GPIO Change Interrupt Flag bit 1 = When at least one of the GPIO <5:0> pins changed state (must be cleared in software) 0 = None of the GPIO <5:0> pins have changed state IOC register must also be enabled. T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before clearing T0IF bit.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
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2.2.2.4 PIE1 Register
Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. The PIE1 register contains the Peripheral Interrupt Enable bits, as shown in Register 2-4.
REGISTER 2-4:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0 ADIE(1) R/W-0 CCP1IE(1) U-0 -- R/W-0 CMIE U-0 -- R/W-0 TMR2IE(1) R/W-0 TMR1IE bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' ADIE: A/D Converter (ADC) Interrupt Enable bit(1) 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt CCP1IE: CCP1 Interrupt Enable bit(1) 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt Unimplemented: Read as `0' CMIE: Comparator Interrupt Enable bit 1 = Enables the Comparator interrupt 0 = Disables the Comparator interrupt Unimplemented: Read as `0' TMR2IE: Timer2 to PR2 Match Interrupt Enable bit(1) 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt
bit 5
bit 4 bit 3
bit 2 bit 1
bit 0
Note 1: PIC12F615/617/HV615 only. PIC12F609/HV609 unimplemented, read as `0'.
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2.2.2.5 PIR1 Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR1 register contains the Peripheral Interrupt flag bits, as shown in Register 2-5.
REGISTER 2-5:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0 ADIF
(1)
R/W-0 CCP1IF
(1)
U-0 --
R/W-0 CMIF
U-0 --
R/W-0 TMR2IF
(1)
R/W-0 TMR1IF bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' ADIF: A/D Interrupt Flag bit(1) 1 = A/D conversion complete 0 = A/D conversion has not completed or has not been started CCP1IF: CCP1 Interrupt Flag bit(1) Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode Unimplemented: Read as `0' CMIF: Comparator Interrupt Flag bit 1 = Comparator output has changed (must be cleared in software) 0 = Comparator output has not changed Unimplemented: Read as `0' TMR2IF: Timer2 to PR2 Match Interrupt Flag bit(1) 1 = Timer2 to PR2 match occurred (must be cleared in software) 0 = Timer2 to PR2 match has not occurred TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software) 0 = Timer1 has not overflowed
bit 5
bit 4 bit 3
bit 2 bit 1
bit 0
Note 1: PIC12F615/617/HV615 only. PIC12F609/HV609 unimplemented, read as `0'.
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2.2.2.6 PCON Register
The Power Control (PCON) register (see Table 12-2) contains flag bits to differentiate between a: * * * * Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset
The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register 2-6.
REGISTER 2-6:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 bit 1
PCON: POWER CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR R/W-0(1) BOR bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Reads as `0' if Brown-out Reset is disabled.
bit 0
Note 1:
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2.2.2.7 APFCON Register (PIC12F615/617/HV615 only)
The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. For this device, the P1A, P1B and Timer1 Gate functions can be moved between different pins. The APFCON register bits are shown in Register 2-7.
REGISTER 2-7:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4
APFCON:ALTERNATE PIN FUNCTION REGISTER(1)
U-0 -- U-0 -- R/W-0 T1GSEL U-0 -- U-0 -- R/W-0 P1BSEL R/W-0 P1ASEL bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' T1GSEL: TMR1 Input Pin Select bit 1 = T1G function is on GP3/T1G(2)/MCLR/VPP 0 = T1G function is on GP4/AN3/CIN1-/T1G/P1B(2)/OSC2/CLKOUT Unimplemented: Read as `0' P1BSEL: P1B Output Pin Select bit 1 = P1B function is on GP4/AN3/CIN1-/T1G/P1B(2)/OSC2/CLKOUT 0 = P1B function is on GP0/AN0/CIN+/P1B/ICSPDAT P1ASEL: P1A Output Pin Select bit 1 = P1A function is on GP5/T1CKI/P1A(2)/OSC1/CLKIN 0 = P1A function is on GP2/AN2/T0CKI/INT/COUT/CCP1/P1A
bit 3-2 bit 1
bit 0
Note 1: PIC12F615/617/HV615 only. 2: Alternate pin function.
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2.3 PCL and PCLATH
2.3.2 STACK
The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in Figure 2-5 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in Figure 2-5 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). The PIC12F609/615/617/12HV609/615 Family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: There are no Status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address.
FIGURE 2-5:
PCH 12 PC 5 8 7
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 0 Instruction with PCL as Destination ALU Result
PCLATH<4:0>
8
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 OPCODE <10:0> PCLATH 11 10 8 7 PCL 0 GOTO, CALL
2.4
Indirect Addressing, INDF and FSR Registers
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR and the IRP bit of the STATUS register, as shown in Figure 2-6. A simple program to clear RAM location 40h-7Fh using indirect addressing is shown in Example 2-1.
2.3.1
MODIFYING PCL
Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<12:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 5 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 13 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). Care should be exercised when jumping into a look-up table or program branch table (computed GOTO) by modifying the PCL register. Assuming that PCLATH is set to the table start address, if the table length is greater than 255 instructions or if the lower 8 bits of the memory address rolls over from 0xFF to 0x00 in the middle of the table, then PCLATH must be incremented for each address rollover that occurs between the table beginning and the target location within the table. For more information refer to Application Note AN556, "Implementing a Table Read" (DS00556).
EXAMPLE 2-1:
MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE
INDIRECT ADDRESSING
0x40 FSR INDF FSR FSR,7 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
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FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC12F609/615/617/12HV609/615
Indirect Addressing 0 IRP(1) 7 File Select Register 0 Direct Addressing RP1(1) RP0 6 From Opcode
Bank Select
Location Select 00 00h 01 10 11
Bank Select 180h
Location Select
Data Memory
NOT USED(2)
7Fh Bank 0 For memory map detail, see Figure 2-3. Note 1: 2: The RP1 and IRP bits are reserved; always maintain these bits clear. Accesses in this area are mirrored back into Bank 0 and Bank 1. Bank 1 Bank 2 Bank 3
1FFh
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3.0 FLASH PROGRAM MEMORY SELF READ/SELF WRITE CONTROL (FOR PIC12F617 ONLY)
3.1 PMADRH and PMADRL Registers
The PMADRH and PMADRL registers can address up to a maximum of 8K words of program memory. When selecting a program address value, the Most Significant Byte (MSB) of the address is written to the PMADRH register and the Least Significant Byte (LSB) is written to the PMADRL register.
The Flash program memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (see Registers 3-1 to 3-5). There are six SFRs used to read and write this memory: * * * * * * PMCON1 PMCON2 PMDATL PMDATH PMADRL PMADRH
3.2
PMCON1 and PMCON2 Registers
PMCON1 is the control register for the data program memory accesses. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental premature termination of a write operation. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. PMCON2 is not a physical register. Reading PMCON2 will read all `0's. The PMCON2 register is used exclusively in the Flash memory write sequence.
When interfacing the program memory block, the PMDATL and PMDATH registers form a two-byte word which holds the 14-bit data for read/write, and the PMADRL and PMADRH registers form a two-byte word which holds the 13-bit address of the Flash location being accessed. These devices have 2K words of program Flash with an address range from 0000h to 07FFh. The program memory allows single word read and a by four word write. A four word write automatically erases the row of the location and writes the new data (erase before write). The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. When the device is code-protected, the CPU may continue to read and write the Flash program memory. Depending on the settings of the Flash Program Memory Enable (WRT<1:0>) bits, the device may or may not be able to write certain blocks of the program memory, however, reads of the program memory are allowed. When the Flash program memory Code Protection (CP) bit in the Configuration Word register is enabled, the program memory is code-protected, and the device programmer (ICSPTM) cannot access data or program memory.
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REGISTER 3-1:
R/W-0 PMDATL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PMDATL: PROGRAM MEMORY DATA REGISTER
R/W-0 PMDATL6 R/W-0 PMDATL5 R/W-0 PMDATL4 R/W-0 PMDATL3 R/W-0 PMDATL2 R/W-0 PMDATL1 R/W-0 PMDATL0 bit 0
PMDATL<7:0>: 8 Least Significant Address bits to Write or Read from Program Memory
REGISTER 3-2:
R/W-0 PMADRL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
PMADRL: PROGRAM MEMORY ADDRESS REGISTER
R/W-0 PMADRL6 R/W-0 PMADRL5 R/W-0 PMADRL4 R/W-0 PMADRL3 R/W-0 PMADRL2 R/W-0 PMADRL1 R/W-0 PMADRL0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PMADRL<7:0>: 8 Least Significant Address bits for Program Memory Read/Write Operation
REGISTER 3-3:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER
U-0 -- R/W-0 PMDATH5 R/W-0 PMDATH4 R/W-0 PMDATH3 R/W-0 PMDATH2 R/W-0 PMDATH1 R/W-0 PMDATH0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' PMDATH<5:0>: 6 Most Significant Data bits from Program Memory
REGISTER 3-4:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 3 bit 2-0
PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 PMADRH2 R/W-0 PMADRH1 R/W-0 PMADRH0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' PMADRH<2:0>: Specifies the 3 Most Significant Address bits or high bits for program memory reads.
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REGISTER 3-5:
U-1 -- bit 7 bit 7 bit 6-3 bit 2 Unimplemented: Read as `1' Unimplemented: Read as `0' WREN: Program Memory Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM WR: Write Control bit 1 = Initiates a write cycle to program memory. (The bit is cleared by hardware when write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the Flash memory is complete RD: Read Control bit 1 = Initiates a program memory read (The read takes one cycle. The RD is cleared in hardware; the RD bit can only be set (not cleared) in software). 0 = Does not initiate a Flash memory read
PMCON1 - PROGRAM MEMORY CONTROL REGISTER 1 (ADDRESS: 93h)
U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
bit 1
bit 0
Legend: R = Readable bit -n = Value at POR W = Writable bit 1 = bit is set U = Unimplemented bit, read as `0' 0 = bit is cleared x = bit is unknown
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3.3 Reading the Flash Program Memory
To read a program memory location, the user must write two bytes of the address to the PMADRL and PMADRH registers, and then set control bit RD (PMCON1<0>). Once the read control bit is set, the program memory Flash controller will use the second instruction cycle after to read the data. This causes the second instruction immediately following the "BSF PMCON1,RD" instruction to be ignored. The data is available in the very next cycle in the PMDATL and PMDATH registers; it can be read as two bytes in the following instructions. PMDATL and PMDATH registers will hold this value until another read or until it is written to by the user (during a write operation).
EXAMPLE 3-1:
BANKSEL MOVLW MOVWF MOVLW MOVWF BANKSEL BSF NOP NOP
FLASH PROGRAM READ
; ; ; ; ; ; ; Change STATUS bits RP1:0 to select bank with PMADRL MS Byte of Program Address to read LS Byte of Program Address to read Bank to containing PMCON1 PM Read
PM_ADR MS_PROG_PM_ADDR PMADRH LS_PROG_PM_ADDR PMADRL PMCON1 PMCON1, RD
; First instruction after BSF PMCON1,RD executes normally ; ; ; ; ; ; Any instructions here are ignored as program memory is read in second cycle after BSF PMCON1,RD Bank to containing PMADRL W = LS Byte of Program PMDATL W = MS Byte of Program PMDATL
BANKSEL PMDATL MOVF PMDATL, W MOVF PMDATH, W
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FIGURE 3-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Flash ADDR
PC
PC + 1
PMADRH,PMADRL
PC+3 PC + 3
PC + 4
PC + 5
Flash DATA
INSTR (PC)
INSTR (PC + 1)
PMDATH,PMDATL
INSTR (PC + 3)
INSTR (PC + 4)
INSTR (PC - 1) Executed here
BSF PMCON1,RD Executed here
INSTR (PC + 1) Executed here
NOP Executed here
INSTR (PC + 3) Executed here
INSTR (PC + 4) Executed here
RD bit
PMDATH PMDATL Register PMRHLT
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3.4 Writing the Flash Program Memory
which the erase takes place (i.e., the last word of the sixteen-word block erase). This is not Sleep mode as the clocks and peripherals will continue to run. After the four-word write cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction. The above sequence must be repeated for the higher 12 words.
A word of the Flash program memory may only be written to if the word is in an unprotected segment of memory. Flash program memory must be written in four-word blocks. See Figure 3-2 and Figure 3-3 for more details. A block consists of four words with sequential addresses, with a lower boundary defined by an address, where PMADRL<1:0> = 00. All block writes to program memory are done as 16-word erase by fourword write operations. The write operation is edgealigned and cannot occur across boundaries. To write program data, it must first be loaded into the buffer registers (see Figure 3-2). This is accomplished by first writing the destination address to PMADRL and PMADRH and then writing the data to PMDATL and PMDATH. After the address and data have been set up, then the following sequence of events must be executed: 1. 2. Write 55h, then AAh, to PMCON2 (Flash programming sequence). Set the WR control bit of the PMCON1 register.
3.5
Protection Against Spurious Write
There are conditions when the device should not write to the program memory. To protect against spurious writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) prevents program memory writes. The write initiate sequence and the WREN bit help prevent an accidental write during brown-out, power glitch or software malfunction.
3.6
Operation During Code-Protect
When the device is code-protected, the CPU is able to read and write unscrambled data to the program memory. The test mode access is disabled.
All four buffer register locations should be written to with correct data. If less than four words are being written to in the block of four words, then a read from the program memory location(s) not being written to must be performed. This takes the data from the program location(s) not being written and loads it into the PMDATL and PMDATH registers. Then the sequence of events to transfer data to the buffer registers must be executed. To transfer data from the buffer registers to the program memory, the PMADRL and PMADRH must point to the last location in the four-word block (PMADRL<1:0> = 11). Then the following sequence of events must be executed: 1. 2. Write 55h, then AAh, to PMCON2 (Flash programming sequence). Set control bit WR of the PMCON1 register to begin the write operation.
3.7
Operation During Write Protect
When the program memory is write-protected, the CPU can read and execute from the program memory. The portions of program memory that are write protected can be modified by the CPU using the PMCON registers, but the protected program memory cannot be modified using ICSP mode.
The user must follow the same specific sequence to initiate the write for each word in the program block, writing each program word in sequence (000, 001, 010, 011). When the write is performed on the last word (PMADRL<1:0> = 11), a block of sixteen words is automatically erased and the content of the four-word buffer registers are written into the program memory. After the "BSF PMCON1,WR" instruction, the processor requires two cycles to set up the erase/write operation. The user must place two NOP instructions after the WR bit is set. Since data is being written to buffer registers, the writing of the first three words of the block appears to occur immediately. The processor will halt internal operations for the typical 4 ms, only during the cycle in
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FIGURE 3-2: BLOCK WRITES TO 2K FLASH PROGRAM MEMORY
7 5 PMDATH 07 PMDATL 0 If at a new row sixteen words of Flash are erased, then four buffers are transferred to Flash automatically after this word is written
6
First word of block to be written
8
14
PMADRL<1:0> = 00 Buffer Register PMADRL<1:0> = 01
14
PMADRL<1:0> = 10
14
PMADRL<1:0> = 11
14
Buffer Register
Buffer Register
Buffer Register
Program Memory
FIGURE 3-3:
FLASH PROGRAM MEMORY LONG WRITE CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash ADDR
PC + 1
PMADRH,PMADRL
PC + 2
PC + 3
PC + 4
Flash DATA
INSTR (PC)
INSTR (PC + 1)
ignored read
PMDATH,PMDATL
INSTR (PC+2)
INSTR (PC+3)
BSF PMCON1,WR INSTR (PC + 1) Executed here Executed here
Processor halted PM Write Time
NOP Executed here
(INSTR (PC + 2) NOP INSTR (PC + 3) Executed here Executed here
Flash Memory Location
WR bit
PMWHLT
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An example of the complete four-word write sequence is shown in Example 3-2. The initial address is loaded into the PMADRH and PMADRL register pair; the eight words of data are loaded using indirect addressing.
EXAMPLE 3-2:
WRITING TO FLASH PROGRAM MEMORY
LOOP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; This write routine assumes the following: ; A valid starting address (the least significant bits = '00') ; is loaded in ADDRH:ADDRL ; ADDRH, ADDRL and DATADDR are all located in data memory ; BANKSEL PMADRH MOVF ADDRH,W ; Load initial address MOVWF PMADRH ; MOVF ADDRL,W ; MOVWF PMADRL ; MOVF DATAADDR,W ; Load initial data address MOVWF FSR ; MOVF INDF,W ; Load first data byte into lower MOVWF PMDATL ; INCF FSR,F ; Next byte MOVF INDF,W ; Load second data byte into upper MOVWF PMDATH ; INCF FSR,F ; BANKSEL PMCON1 BSF PMCON1,WREN ; Enable writes BCF INTCON,GIE ; Disable interrupts (if using) BTFSC INTCON,GIE ; See AN576 GOTO $-2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Required Sequence MOVLW 55h ; Start of required write sequence: MOVWF PMCON2 ; Write 55h MOVLW 0AAh ; MOVWF PMCON2 ; Write 0AAh BSF PMCON1,WR ; Set WR bit to begin write NOP ; Required to transfer data to the buffer NOP ; registers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; BCF PMCON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts (comment out if not using interrupts) BANKSEL PMADRL MOVF PMADRL, W INCF PMADRL,F ; Increment address ANDLW 0x03 ; Indicates when sixteen words have been programmed SUBLW 0x03 ; 0x0F = 16 words ; 0x0B = 12 words ; 0x07 = 8 words ; 0x03 = 4 words BTFSS STATUS,Z ; Exit on a match, GOTO LOOP ; Continue if more data needs to be written
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TABLE 3-1:
Name PMCON1 PMCON2 PMADRL PMADRH PMDATL PMDATH Legend: Bit 7 --
SUMMARY OF REGISTERS ASSOCIATED WITH PROGRAM MEMORY
Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 -- Bit 2 WREN Bit 1 WR Bit 0 RD Value on POR, BOR ---- -000 ---- ---PMADRL2 PMADRH2 PMDATL2 PMDATH2 PMADRL1 PMADRH1 PMDATL1 PMDATH1 PMADRL0 PMADRH0 PMDATL0 PMDATH0 0000 0000 ---- -000 0000 0000 --00 0000 Value on all other Resets ---- -000 ---- ---0000 0000 ---- -000 0000 0000 --00 0000
Program Memory Control Register 2 (not a physical register) PMADRL7 PMADRL6 PMADRL5 -- -- -- PMDATL5 PMDATH5 PMADRL4 -- PMDATL4 PMDATH4 PMADRL3 -- PMDATL3 PMDATH3
PMDATL7 PMDATL6 -- --
x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends upon condition. Shaded cells are not used by Program Memory module.
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NOTES:
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4.0
4.1
OSCILLATOR MODULE
Overview
The Oscillator module can be configured in one of eight clock modes. EC - External clock with I/O on OSC2/CLKOUT. LP - 32 kHz Low-Power Crystal mode. XT - Medium Gain Crystal or Ceramic Resonator Oscillator mode. 6. HS - High Gain Crystal or Ceramic Resonator mode. 7. RC - External Resistor-Capacitor (RC) with FOSC/4 output on OSC2/CLKOUT. 8. RCIO - External Resistor-Capacitor (RC) with I/O on OSC2/CLKOUT. 9. INTOSC - Internal oscillator with FOSC/4 output on OSC2 and I/O on OSC1/CLKIN. 10. INTOSCIO - Internal oscillator with I/O on OSC1/CLKIN and OSC2/CLKOUT. Clock Source modes are configured by the FOSC<2:0> bits in the Configuration Word register (CONFIG). The Internal Oscillator module provides a selectable system clock mode of either 4 MHz (Postscaler) or 8 MHz (INTOSC). 3. 4. 5.
The Oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 4-1 illustrates a block diagram of the Oscillator module. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured with a choice of two selectable speeds: internal or external system clock source.
FIGURE 4-1:
PIC(R) MCU CLOCK SOURCE BLOCK DIAGRAM
External Oscillator OSC2 Sleep OSC1
FOSC<2:0> IOSCFS<7> (Configuration Word Register)
LP, XT, HS, RC, RCIO, EC MUX
INTOSC Internal Oscillator
System Clock (CPU and Peripherals)
INTOSC 8 MHz
Postscaler 4 MHz
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4.2 Clock Source Modes 4.3
4.3.1
External Clock Modes
OSCILLATOR START-UP TIMER (OST)
Clock Source modes can be classified as external or internal. * External Clock modes rely on external circuitry for the clock source. Examples are: Oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. * Internal clock sources are contained internally within the Oscillator module. The Oscillator module has two selectable clock frequencies: 4 MHz and 8 MHz The system clock can be selected between external or internal clock sources via the FOSC<2:0> bits of the Configuration Word register.
If the Oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the Oscillator module. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 4-1.
TABLE 4-1:
Switch From Sleep/POR Sleep/POR Sleep/POR
OSCILLATOR DELAY EXAMPLES
Switch To INTOSC EC, RC LP, XT, HS Frequency 125 kHz to 8 MHz DC - 20 MHz 32 kHz to 20 MHz Oscillator Delay Oscillator Warm-Up Delay (TWARM) 2 instruction cycles 1024 Clock Cycles (OST)
4.3.2
EC MODE
The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input and the OSC2 is available for general purpose I/O. Figure 4-2 shows the pin connections for EC mode. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC(R) MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.
FIGURE 4-2:
EXTERNAL CLOCK (EC) MODE OPERATION
OSC1/CLKIN PIC(R) MCU I/O OSC2/CLKOUT(1)
Clock from Ext. System
Note 1:
Alternate pin functions are listed in the Section 1.0 "Device Overview".
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4.3.3 LP, XT, HS MODES
The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 4-3). The mode selects a low, medium or high gain setting of the internal inverteramplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals). XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure 4-3 and Figure 4-4 show typical circuits for quartz crystal and ceramic resonators, respectively. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Applications Notes: * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPIC(R) and PIC(R) Devices" (DS00826) * AN849, "Basic PIC(R) Oscillator Design" (DS00849) * AN943, "Practical PIC(R) Oscillator Analysis and Design" (DS00943) * AN949, "Making Your Oscillator Work" (DS00949)
FIGURE 4-4:
CERAMIC RESONATOR OPERATION (XT OR HS MODE)
PIC(R) MCU
OSC1/CLKIN
FIGURE 4-3:
QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE)
PIC(R) MCU
OSC1/CLKIN C1
To Internal Logic RP(3) RF(2) Sleep
C1 Quartz Crystal
To Internal Logic RF(2) Sleep C2 Ceramic RS(1) Resonator OSC2/CLKOUT
C2
RS(1)
OSC2/CLKOUT
Note 1:
A series resistor (RS) may be required for ceramic resonators with low drive level.
Note 1: 2:
A series resistor (RS) may be required for quartz crystals with low drive level. The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M.
2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation.
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4.3.4 EXTERNAL RC MODES
4.4
Internal Clock Modes
The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO. In RC mode, the RC circuit connects to OSC1. OSC2/ CLKOUT outputs the RC oscillator frequency divided by 4. This signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. Figure 4-5 shows the external RC mode connections.
The Oscillator module provides a selectable system clock source of either 4 MHz or 8 MHz. The selectable frequency is configured through the IOSCFS bit of the Configuration Word. The frequency of the internal oscillator can be trimmed with a calibration value in the OSCTUNE register.
4.4.1
INTOSC AND INTOSCIO MODES
FIGURE 4-5:
VDD REXT
EXTERNAL RC MODES
PIC(R) MCU
The INTOSC and INTOSCIO modes configure the internal oscillators as the system clock source when the device is programmed using the oscillator selection or the FOSC<2:0> bits in the Configuration Word register (CONFIG). See Section 12.0 "Special Features of the CPU" for more information. In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT outputs the selected internal oscillator frequency divided by 4. The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT are available for general purpose I/O.
OSC1/CLKIN CEXT VSS FOSC/4 or I/O(2) OSC2/CLKOUT
(1)
Internal Clock
Recommended values: 10 k REXT 100 k, <3V 3 k REXT 100 k, 3-5V CEXT > 20 pF, 2-5V Note 1: 2: Alternate pin functions are listed in Section 1.0 "Device Overview". Output depends upon RC or RCIO Clock mode.
In RCIO mode, the RC circuit is connected to OSC1. OSC2 becomes an additional general purpose I/O pin. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: * threshold voltage variation * component tolerances * packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used.
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4.4.1.1 OSCTUNE Register
The oscillator is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 4-1). The default value of the OSCTUNE register is `0'. The value is a 5-bit two's complement number. When the OSCTUNE register is modified, the frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.
REGISTER 4-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0 -- U-0 -- R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency 01110 = * * * 00001 = 00000 = Oscillator module is running at the calibrated frequency. 11111 = * * * 10000 = Minimum frequency
TABLE 4-2:
Name CONFIG(2) OSCTUNE Legend: Note 1: 2:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Bit 7 IOSCFS -- Bit 6 CP -- Bit 5 MCLRE -- Bit 4 PWRTE TUN4 Bit 3 WDTE TUN3 Bit 2 FOSC2 TUN2 Bit 1 FOSC1 TUN1 Bit 0 FOSC0 TUN0 Value on POR, BOR -- ---0 0000 Value on all other Resets(1) -- ---u uuuu
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by oscillators. Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. See Configuration Word register (Register 12-1) for operation of all register bits.
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5.0 I/O PORT
There are as many as six general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. Reading the GPIO register (Register 5-1) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. GP3 reads `0' when MCLRE = 1. The TRISIO register controls the direction of the GPIO pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISIO register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. Note: The ANSEL register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0' and cannot generate an interrupt.
5.1
GPIO and the TRISIO Registers
GPIO is a 6-bit wide port with 5 bidirectional and 1 inputonly pin. The corresponding data direction register is TRISIO (Register 5-2). Setting a TRISIO bit (= 1) will make the corresponding GPIO pin an input (i.e., disable the output driver). Clearing a TRISIO bit (= 0) will make the corresponding GPIO pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is GP3, which is input only and its TRIS bit will always read as `1'. Example 51 shows how to initialize GPIO.
EXAMPLE 5-1:
BANKSEL CLRF BANKSEL CLRF MOVLW MOVWF GPIO GPIO ANSEL ANSEL 0Ch TRISIO
INITIALIZING GPIO
; ;Init GPIO ; ;digital I/O, ADC clock ;setting `don't care' ;Set GP<3:2> as inputs ;and set GP<5:4,1:0> ;as outputs
Note:
GPIO = PORTA TRISIO = TRISA
REGISTER 5-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
GPIO: GPIO REGISTER
U-0 -- R/W-x GP5 R/W-x GP4 R-x GP3 R/W-x GP2 R/W-x GP1 R/W-x GP0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' GP<5:0>: GPIO I/O Pin bit 1 = GPIO pin is > VIH 0 = GPIO pin is < VIL
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REGISTER 5-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TRISIO: GPIO TRI-STATE REGISTER
U-0 -- R/W-1 TRISIO5 R/W-1 TRISIO4 R-1 TRISIO3 R/W-1 TRISIO2 R/W-1 TRISIO1 R/W-1 TRISIO0 bit 0
Unimplemented: Read as `0' TRISIO<5:0>: GPIO Tri-State Control bit 1 = GPIO pin configured as an input (tri-stated) 0 = GPIO pin configured as an output TRISIO<3> always reads `1'. TRISIO<5:4> always reads `1' in XT, HS and LP Oscillator modes.
Note 1: 2:
5.2
Additional Pin Functions
Every GPIO pin on the PIC12F609/615/617/12HV609/ 615 has an interrupt-on-change option and a weak pullup option. The next three sections describe these functions.
For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of GPIO. The `mismatch' outputs of the last read are OR'd together to set the GPIO Change Interrupt Flag bit (GPIF) in the INTCON register (Register 2-3). This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by: a) Any read of GPIO AND Clear flag bit GPIF. This will end the mismatch condition; OR b) Any write of GPIO AND Clear flag bit GPIF will end the mismatch condition;
5.2.1
ANSEL REGISTER
The ANSEL register is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSEL bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSEL bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port.
5.2.2
WEAK PULL-UPS
A mismatch condition will continue to set flag bit GPIF. Reading GPIO will end the mismatch condition and allow flag bit GPIF to be cleared. The latch holding the last read value is not affected by a MCLR nor BOR Reset. After these resets, the GPIF flag will continue to be set if a mismatch is present. Note: If a change on the I/O pin should occur when any GPIO operation is being executed, then the GPIF interrupt flag may not get set.
Each of the GPIO pins, except GP3, has an individually configurable internal weak pull-up. Control bits WPUx enable or disable each pull-up. Refer to Register 5-5. Each weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset by the GPPU bit of the OPTION register). A weak pull-up is automatically enabled for GP3 when configured as MCLR and disabled when GP3 is an I/O. There is no software control of the MCLR pull-up.
5.2.3
INTERRUPT-ON-CHANGE
Each GPIO pin is individually configurable as an interrupt-on-change pin. Control bits IOCx enable or disable the interrupt function for each pin. Refer to Register 5-6. The interrupt-on-change is disabled on a Power-on Reset.
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REGISTER 5-3:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4 bit 3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ANSEL: ANALOG SELECT REGISTER (PIC12F609/HV609)
U-0 -- U-0 -- U-0 -- R/W-1 ANS3 U-0 -- R/W-1 ANS1 R/W-1 ANS0 bit 0
Unimplemented: Read as `0' ANS3: Analog Select Between Analog or Digital Function on Pin GP4 1 = Analog input. Pin is assigned as analog input(1). 0 = Digital I/O. Pin is assigned to port or special function. Unimplemented: Read as `0' ANS1: Analog Select Between Analog or Digital Function on Pin GP1 1 = Analog input. Pin is assigned as analog input.(1) 0 = Digital I/O. Pin is assigned to port or special function. ANS0: Analog Select Between Analog or Digital Function on Pin GP0 0 = Digital I/O. Pin is assigned to port or special function. 1 = Analog input. Pin is assigned as analog input.(1) Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-onchange if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin.
bit 2 bit 1
bit 0
Note 1:
REGISTER 5-4:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-4
ANSEL: ANALOG SELECT REGISTER (PIC12F615/617/HV615)
R/W-1 ADCS2 R/W-1 ADCS1 R/W-1 ADCS0 R/W-1 ANS3 R/W-1 ANS2 R/W-1 ANS1 R/W-1 ANS0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 ANS<3:0>: Analog Select Between Analog or Digital Function on Pins GP4, GP2, GP1, GP0, respectively. 1 = Analog input. Pin is assigned as analog input(1). 0 = Digital I/O. Pin is assigned to port or special function. Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-onchange if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin.
bit 3-0
Note 1:
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REGISTER 5-5:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
WPU: WEAK PULL-UP GPIO REGISTER
U-0 -- R/W-1 WPU5 R/W-1 WPU4 U-0 -- R/W-1 WPU2 R/W-1 WPU1 R/W-1 WPU0 bit 0
Unimplemented: Read as `0' WPU<5:4>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled WPU<3>: Weak Pull-up Register bit(3) WPU<2:0>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled Global GPPU must be enabled for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in Output mode (TRISIO = 0). The GP3 pull-up is enabled when configured as MCLR in the Configuration Word, otherwise it is disabled as an input and reads as `0'. WPU<5:4> always reads `1' in XT, HS and LP Oscillator modes.
bit 3 bit 2-0
Note 1: 2: 3: 4:
REGISTER 5-6:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
IOC: INTERRUPT-ON-CHANGE GPIO REGISTER
U-0 -- R/W-0 IOC5 R/W-0 IOC4 R/W-0 IOC3 R/W-0 IOC2 R/W-0 IOC1 R/W-0 IOC0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' IOC<5:0>: Interrupt-on-change GPIO Control bit 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized. IOC<5:4> always reads `1' in XT, HS and LP Oscillator modes.
Note 1: 2:
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5.2.4 PIN DESCRIPTIONS AND DIAGRAMS 5.2.4.2 GP1/AN1(1)/CIN0-/VREF(1)/ICSPCLK
Each GPIO pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the Comparator or the ADC, refer to the appropriate section in this data sheet. Figure 5-1 shows the diagram for this pin. The GP1 pin is configurable to function as one of the following: * * * * * a general purpose I/O an analog input for the ADC(1) an analog inverting input to the comparator a voltage reference input for the ADC(1) In-Circuit Serial Programming clock
5.2.4.1
GP0/AN0(1)/CIN+/P1B(1)/ICSPDAT
Figure 5-1 shows the diagram for this pin. The GP0 pin is configurable to function as one of the following: * * * * * a general purpose I/O an analog input for the ADC(1) an analog non-inverting input to the comparator a PWM output(1) In-Circuit Serial Programming data
Note 1:
PIC12F615/617/HV615 only.
FIGURE 5-1:
BLOCK DIAGRAM OF GP<1:0>
Analog(1) Input Mode VDD Data Bus D WR WPU RD WPU D WR GPIO Q I/O Pin VSS Q Weak GPPU VDD CK Q
CK Q
D WR TRISIO RD TRISIO RD GPIO D WR IOC RD IOC Q Interrupt-onChange S(2) R
Q
CK Q
Analog(1) Input Mode
Q Q D EN Q D EN Q1
CK Q
From other GP<5:0> pins (GP0) GP<5:2, 0> pins (GP1)
RD GPIO To Comparator To A/D Converter(3)
Write `0' to GBIF
Note
1: 2: 3:
Comparator mode and ANSEL determines Analog Input mode. Set has priority over Reset. PIC12F615/617/HV615 only.
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5.2.4.3 GP2/AN2(1)/T0CKI/INT/COUT/ CCP1(1)/P1A(1)
Figure 5-2 shows the diagram for this pin. The GP2 pin is configurable to function as one of the following: * * * * * * * a general purpose I/O an analog input for the ADC(1) the clock input for TMR0 an external edge triggered interrupt a digital output from Comparator a Capture input/Compare input/PWM output(1) a PWM output(1) Note 1: PIC12F615/617/HV615 only.
FIGURE 5-2:
BLOCK DIAGRAM OF GP2
Analog(1) Input Mode VDD Data Bus D WR WPU RD WPU C1OE D WR GPIO Q 1 0 I/O Pin VSS Q C1OE Enable Weak GPPU VDD CK Q
CK Q
D WR TRISIO RD TRISIO RD GPIO D WR IOC RD IOC Q Interrupt-onChange S(2) R
Q
CK Q
Analog(1) Input Mode
Q Q D EN Q D EN Q1
CK Q
From other GP<5:3, 1:0> pins To Timer0 To INT
RD GPIO
Write `0' to GBIF
To A/D Converter(3) Note 1: 2: 3: Comparator mode and ANSEL determines Analog Input mode. Set has priority over Reset. PIC12F615/617/HV615 only.
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5.2.4.4 GP3/T1G(1, 2)/MCLR/VPP
Figure 5-3 shows the diagram for this pin. The GP3 pin is configurable to function as one of the following: * a general purpose input * a Timer1 gate (count enable), alternate pin(1, 2) * as Master Clear Reset with weak pull-up Note 1: Alternate pin function. 2: PIC12F615/617/HV615 only.
FIGURE 5-3:
BLOCK DIAGRAM OF GP3
VDD MCLRE Weak
Data Bus Reset RD TRISIO RD GPIO D WR IOC RD IOC Q Interrupt-onChange S(1) R From other
GP<5:4, 2:0> pins
MCLRE Input Pin MCLRE VSS
VSS
Q Q Q EN Q D EN Q1 D
CK
RD GPIO Write `0' to GBIF
Note 1:
Set has priority over Reset
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5.2.4.5 GP4/AN3(2)/CIN1-/T1G/ P1B(1, 2)/OSC2/CLKOUT
Figure 5-4 shows the diagram for this pin. The GP4 pin is configurable to function as one of the following: * * * * a general purpose I/O an analog input for the ADC(2) Comparator inverting input a Timer1 gate (count enable) * PWM output, alternate pin(1, 2) * a crystal/resonator connection * a clock output Note 1: Alternate pin function. 2: PIC12F615/617/HV615 only.
FIGURE 5-4:
BLOCK DIAGRAM OF GP4
Analog(3) Input Mode Data Bus WR WPU RD WPU OSC1 D Q CLK(1) Modes VDD Weak GPPU Oscillator Circuit CLKOUT Enable D WR GPIO Q FOSC/4 1 0 CLKOUT Enable D WR TRISIO RD TRISIO RD GPIO D WR IOC RD IOC Q S(4) R From other
GP<5, 3:0> pins
CK Q
VDD
CK Q
I/O Pin
Q
VSS INTOSC/ RC/EC(2) CLKOUT Enable Analog Input Mode
CK Q
Q Q D EN Q D EN Q1
CK Q
Interrupt-onChange
RD GPIO
Write `0' to GBIF
To T1G To A/D Converter(5)
Note 1: CLK modes are XT, HS, LP, TMR1 LP and CLKOUT Enable. 2: With CLKOUT option. 3: Analog Input mode comes from ANSEL. 4: Set has priority over Reset. 5: PIC12F615/617/HV615 only.
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5.2.4.6 GP5/T1CKI/P1A(1, 2)/OSC1/CLKIN
Note 1: Alternate pin function. 2: PIC12F615/617/HV615 only. Figure 5-5 shows the diagram for this pin. The GP5 pin is configurable to function as one of the following: * * * * * a general purpose I/O a Timer1 clock input PWM output, alternate pin(1, 2) a crystal/resonator connection a clock input
FIGURE 5-5:
BLOCK DIAGRAM OF GP5
INTOSC Mode Data Bus D WR WPU RD WPU CK Q Q GPPU Oscillator Circuit OSC2 D WR GPIO CK Q Q VDD TMR1LPEN(1) VDD Weak
I/O Pin D WR TRISIO RD TRISIO RD GPIO D WR IOC RD IOC Q Q Interrupt-onChange S(2) R From other GP<4:0> pins RD GPIO Write `0' to GBIF To Timer1 Note 1: 2: Timer1 LP Oscillator enabled. Set has priority over Reset. D EN CK Q Q Q EN Q1 D CK Q Q INTOSC Mode VSS
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TABLE 5-1:
Name ANSEL CMCON0 INTCON IOC OPTION_REG GPIO TRISIO WPU T1CON CCP1CON(1) APFCON(1) Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH GPIO
Bit 7 -- CMON GIE -- GPPU -- -- -- T1GINV P1M -- Bit 6 ADCS2(1) COUT PEIE -- INTEDG -- -- -- TMR1GE -- -- Bit 5 ADCS1(1) CMOE T0IE IOC5 T0CS GP5 TRISIO5 WPU5 TICKPS1 DC1B1 -- Bit 4 ADCS0(1) CMPOL INTE IOC4 T0SE GP4 TRISIO4 WPU4 T1CKPS0 DC1B0 T1GSEL Bit 3 ANS3 -- GPIE IOC3 PSA GP3 TRISIO3 WPU3 T1OSCEN CCP1M3 -- Bit 2 ANS2(1) CMR T0IF IOC2 PS2 GP2 TRISIO2 WPU2 T1SYNC CCP1M2 -- Bit 1 ANS1 -- INTF IOC1 PS1 GP1 TRISIO1 WPU1 TMR1CS CCP1M1 P1BSEL Bit 0 ANS0 CMCH GPIF IOC0 PS0 GP0 TRISIO0 WPU0 TMR1ON CCP1M0 P1ASEL Value on POR, BOR -000 1111 0000 -0-0 0000 0000 --00 0000 1111 1111 --xx xxxx --11 1111 --11 1111 0000 0000 0-00 0000 ---0 --00 Value on all other Resets -000 1111 0000 -0-0 0000 0000 --00 0000 1111 1111 --u0 u000 --11 1111 --11 -111 uuuu uuuu 0-00 0000 ---0 --00
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by GPIO. PIC12F615/617/HV615 only.
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6.0 TIMER0 MODULE
6.1 Timer0 Operation
The Timer0 module is an 8-bit timer/counter with the following features: * * * * * 8-bit timer/counter register (TMR0) 8-bit prescaler (shared with Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter.
6.1.1
8-BIT TIMER MODE
When used as a timer, the Timer0 module will increment every instruction cycle (without prescaler). Timer mode is selected by clearing the T0CS bit of the OPTION register to `0'. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written.
Figure 6-1 is a block diagram of the Timer0 module.
6.1.2
8-BIT COUNTER MODE
When used as a counter, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. The incrementing edge is determined by the T0SE bit of the OPTION register. Counter mode is selected by setting the T0CS bit of the OPTION register to `1'.
FIGURE 6-1:
FOSC/4
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 0 1 1 T0CKI pin T0SE 0 0 T0CS 1 8 8-bit Prescaler PSA Set Flag bit T0IF on Overflow Sync 2 TCY TMR0 8
PSA
PS<2:0> WDTE Watchdog Timer
1 WDT Time-out 0
PSA
Note 1: 2:
T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. WDTE bit is in the Configuration Word register.
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6.1.3 SOFTWARE PROGRAMMABLE PRESCALER
A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a `0'. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be assigned to the WDT module. The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the prescaler. When the prescaler is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. When changing the prescaler assignment from the WDT to the Timer0 module, the following instruction sequence must be executed (see Example 6-2).
EXAMPLE 6-2:
CLRWDT
CHANGING PRESCALER (WDT TIMER0)
;Clear WDT and ;prescaler BANKSEL OPTION_REG ; MOVLW b'11110000' ;Mask TMR0 select and ANDWF OPTION_REG,W ;prescaler bits IORLW b'00000011' ;Set prescale to 1:16 MOVWF OPTION_REG ;
6.1.4
TIMER0 INTERRUPT
6.1.3.1
Switching Prescaler Between Timer0 and WDT Modules
Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The T0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The T0IF bit must be cleared in software. The Timer0 interrupt enable is the T0IE bit of the INTCON register. Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep.
As a result of having the prescaler assigned to either Timer0 or the WDT, it is possible to generate an unintended device Reset when switching prescaler values. When changing the prescaler assignment from Timer0 to the WDT module, the instruction sequence shown in Example 6-1, must be executed.
6.1.5
USING TIMER0 WITH AN EXTERNAL CLOCK
EXAMPLE 6-1:
BANKSEL CLRWDT CLRF BANKSEL BSF CLRWDT MOVLW ANDWF IORLW MOVWF TMR0 TMR0
CHANGING PRESCALER (TIMER0 WDT)
; ;Clear WDT ;Clear TMR0 and ;prescaler ; ;Select WDT ; ; ;Mask prescaler ;bits ;Set WDT prescaler ;to 1:32
When Timer0 is in Counter mode, the synchronization of the T0CKI input and the Timer0 register is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements as shown in Section 16.0 "Electrical Specifications".
OPTION_REG OPTION_REG,PSA
b'11111000' OPTION_REG,W b'00000101' OPTION_REG
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REGISTER 6-1:
R/W-1 GPPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
OPTION_REG: OPTION REGISTER
R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual PORT latch values in WPU register INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits
BIT VALUE TMR0 RATE WDT RATE 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
TABLE 6-1:
Name TMR0 INTCON OPTION_REG TRISIO Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx INTE T0SE GPIE PSA T0IF PS2 INTF PS1 GPIF PS0 0000 000x 1111 1111 --11 1111 Value on all other Resets uuuu uuuu 0000 000x 1111 1111 --11 1111
Timer0 Module Register GIE GPPU -- PEIE INTEDG -- T0IE T0CS
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0
- = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
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NOTES:
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7.0 TIMER1 MODULE WITH GATE CONTROL
7.2 Clock Source Selection
The TMR1CS bit of the T1CON register is used to select the clock source. When TMR1CS = 0, the clock source is FOSC/4. When TMR1CS = 1, the clock source is supplied externally.
The Timer1 module is a 16-bit timer/counter with the following features: * * * * * * * * * * * 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 3-bit prescaler Optional LP oscillator Synchronous or asynchronous operation Timer1 gate (count enable) via comparator or T1G pin Interrupt on overflow Wake-up on overflow (external clock, Asynchronous mode only) Time base for the Capture/Compare function Special Event Trigger (with ECCP) Comparator output synchronization to Timer1 clock
Clock Source FOSC/4 FOSC T1CKI pin
TMR1CS 0 0 1
T1ACS 0 1 x
Figure 7-1 is a block diagram of the Timer1 module.
7.1
Timer1 Operation
The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer. When used with an external clock source, the module can be used as either a timer or counter.
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FIGURE 7-1: TIMER1 BLOCK DIAGRAM
TMR1GE TMR1ON Set flag bit TMR1IF on Overflow To Comparator Module Timer1 Clock EN 0 Synchronized clock input T1GINV
TMR1(2) TMR1H TMR1L
1
Oscillator
(1)
T1SYNC 1 Prescaler 1, 2, 4, 8 0 Synchronize(3) det
OSC1/T1CKI
OSC2/T1G TMR1CS
2 T1CKPS<1:0> 0
INTOSC Without CLKOUT T1OSCEN
FOSC FOSC/4 Internal Clock
1 1 0 T1ACS COUT T1GSEL(2)
1 0 T1GSS
GP3/T1G(4, 5)
Note 1: 2: 3: 4: 5:
ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI. Timer1 register increments on rising edge. Synchronize does not operate while in Sleep. Alternate pin function. PIC12F615/617/HV615 only.
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7.2.1 INTERNAL CLOCK SOURCE
7.5
When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples of TCY as determined by the Timer1 prescaler.
Timer1 Operation in Asynchronous Counter Mode
7.2.2
EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1 module may work as a timer or a counter. When counting, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. If an external clock oscillator is needed (and the microcontroller is using the INTOSC without CLKOUT), Timer1 can use the LP oscillator as a clock source. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after one or more of the following conditions: * Timer1 is enabled after POR or BOR Reset * A write to TMR1H or TMR1L * T1CKI is high when Timer1 is disabled and when Timer1 is re-enabled T1CKI is low. See Figure 7-2.
If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 7.5.1 "Reading and Writing Timer1 in Asynchronous Counter Mode"). Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce a single spurious increment. In asynchronous counter mode or when using the internal oscillator and T1ACS=1, Timer1 can not be used as a time base for the capture or compare modes of the ECCP module (for PIC12F615/617/ HV615 only).
Note:
7.3
Timer1 Prescaler
7.5.1
Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L.
READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE
7.4
Timer1 Oscillator
Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TTMR1L register pair.
A low-power 32.768 kHz crystal oscillator is built-in between pins OSC1 (input) and OSC2 (output). The oscillator is enabled by setting the T1OSCEN control bit of the T1CON register. The oscillator will continue to run during Sleep. The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer1 can use this mode only when the primary system clock is derived from the internal oscillator or when in LP oscillator mode. The user must provide a software time delay to ensure proper oscillator start-up. TRISIO5 and TRISIO4 bits are set when the Timer1 oscillator is enabled. GP5 and GP4 bits read as `0' and TRISIO5 and TRISIO4 bits read as `1'. Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1.
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7.6 Timer1 Gate 7.9
Timer1 gate source is software configurable to be the T1G pin (or the alternate T1G pin) or the output of the Comparator. This allows the device to directly time external events using T1G or analog events using the Comparator. See the CMCON1 Register (Register 9-2) for selecting the Timer1 gate source. This feature can simplify the software for a Delta-Sigma A/D converter and many other applications. For more information on Delta-Sigma A/D converters, see the Microchip web site (www.microchip.com). Note: TMR1GE bit of the T1CON register must be set to use either T1G or COUT as the Timer1 gate source. See Register 9-2 for more information on selecting the Timer1 gate source.
ECCP Capture/Compare Time Base (PIC12F615/617/HV615 only)
The ECCP module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a Special Event Trigger. For more information, see Section 11.0 "Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only)".
Timer1 gate can be inverted using the T1GINV bit of the T1CON register, whether it originates from the T1G pin or the Comparator output. This configures Timer1 to measure either the active-high or active-low time between events.
7.7
Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: * Timer1 interrupt enable bit of the PIE1 register * PEIE bit of the INTCON register * GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: The TMR1H:TTMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts.
7.8
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: * TMR1ON bit of the T1CON register must be set * TMR1IE bit of the PIE1 register must be set * PEIE bit of the INTCON register must be set The device will wake-up on an overflow and execute the next instruction. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h).
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7.10 ECCP Special Event Trigger (PIC12F615/617/HV615 only)
For more information, see Section 11.0 "Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only)".
If a ECCP is configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1 interrupt. The ECCP module may still be configured to generate a ECCP interrupt. In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for Timer1. Timer1 should be synchronized to the FOSC to utilize the Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the ECCP, the write will take precedence.
7.11
Comparator Synchronization
The same clock used to increment Timer1 can also be used to synchronize the comparator output. This feature is enabled in the Comparator module. When using the comparator for Timer1 gate, the comparator output should be synchronized to Timer1. This ensures Timer1 does not miss an increment if the comparator changes. For more information, see Section 9.0 "Comparator Module".
FIGURE 7-2:
T1CKI = 1 when TMR1 Enabled
TIMER1 INCREMENTING EDGE
T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
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7.12 Timer1 Control Register
The Timer1 Control register (T1CON), shown in Register 7-1, is used to control Timer1 and select the various features of the Timer1 module.
REGISTER 7-1:
R/W-0 T1GINV bit 7 Legend: R = Readable bit -n = Value at POR bit 7
(1)
T1CON: TIMER 1 CONTROL REGISTER
R/W-0 R/W-0
(2)
R/W-0 T1CKPS0
R/W-0 T1OSCEN
R/W-0 T1SYNC
R/W-0 TMR1CS
R/W-0 TMR1ON bit 0
TMR1GE
T1CKPS1
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
T1GINV: Timer1 Gate Invert bit(1) 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) TMR1GE: Timer1 Gate Enable bit(2) If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 is on if Timer1 gate is active 0 = Timer1 is on T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value T1OSCEN: LP Oscillator Enable Control bit If INTOSC without CLKOUT oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off For all other system clock modes: This bit is ignored. LP oscillator is disabled. T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) or system clock (FOSC)(3) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 T1GINV bit inverts the Timer1 gate logic, regardless of source. TMR1GE bit must be set to use either T1G pin or COUT, as selected by the T1GSS bit of the CMCON1 register, as a Timer1 gate source. See T1ACS bit in CMCON1 register.
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
Note 1: 2: 3:
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TABLE 7-1:
Name APFCON(1) CMCON0 CMCON1 INTCON PIE1 PIR1 TMR1H TMR1L T1CON Legend: Note 1: Bit 7 -- CMON -- GIE -- --
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Bit 6 -- COUT -- PEIE ADIE(1) ADIF(1) Bit 5 -- CMOE -- T0IE CCP1IE(1) CCP1IF(1) Bit 4 T1GSEL CMPOL T1ACS INTE -- -- Bit 3 -- -- CMHYS GPIE CMIE CMIF Bit 2 -- CMR -- T0IF -- -- Bit 1 P1BSEL -- T1GSS INTF TMR2IE(1) TMR2IF(1) Bit 0 P1ASEL CMCH CMSYNC GPIF TMR1IE TMR1IF Value on POR, BOR ---0 --00 0000 -0-0 ---0 0-10 0000 000x -00- 0-00 -00- 0-00 xxxx xxxx xxxx xxxx TMR1CS TMR1ON 0000 0000 Value on all other Resets ---0 --00 0000 -0-0 ---0 0-10 0000 000x -00- 0-00 -00- 0-00 uuuu uuuu uuuu uuuu uuuu uuuu
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module. PIC12F615/617/HV615 only.
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NOTES:
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8.0 TIMER2 MODULE (PIC12F615/617/HV615 ONLY)
The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a `1'. Timer2 is turned off by clearing the TMR2ON bit to a `0'. The Timer2 prescaler is controlled by the T2CKPS bits in the T2CON register. The Timer2 postscaler is controlled by the TOUTPS bits in the T2CON register. The prescaler and postscaler counters are cleared when: * A write to TMR2 occurs. * A write to T2CON occurs. * Any device Reset occurs (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset). Note: TMR2 is not cleared when T2CON is written.
The Timer2 module is an 8-bit timer with the following features: * * * * * 8-bit timer register (TMR2) 8-bit period register (PR2) Interrupt on TMR2 match with PR2 Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16)
See Figure 8-1 for a block diagram of Timer2.
8.1
Timer2 Operation
The clock input to the Timer2 module is the system instruction clock (FOSC/4). The clock is fed into the Timer2 prescaler, which has prescale options of 1:1, 1:4 or 1:16. The output of the prescaler is then used to increment the TMR2 register. The values of TMR2 and PR2 are constantly compared to determine when they match. TMR2 will increment from 00h until it matches the value in PR2. When a match occurs, two things happen: * TMR2 is reset to 00h on the next increment cycle. * The Timer2 postscaler is incremented The match output of the Timer2/PR2 comparator is then fed into the Timer2 postscaler. The postscaler has postscale options of 1:1 to 1:16 inclusive. The output of the Timer2 postscaler is used to set the TMR2IF interrupt flag bit in the PIR1 register.
FIGURE 8-1:
TIMER2 BLOCK DIAGRAM
TMR2 Output Sets Flag bit TMR2IF
FOSC/4
Prescaler 1:1, 1:4, 1:16 2 T2CKPS<1:0>
TMR2
Reset
Comparator EQ PR2
Postscaler 1:1 to 1:16 4 TOUTPS<3:0>
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REGISTER 8-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
T2CON: TIMER 2 CONTROL REGISTER
R/W-0 R/W-0 TOUTPS2 R/W-0 TOUTPS1 R/W-0 TOUTPS0 R/W-0 TMR2ON R/W-0 T2CKPS1 R/W-0 T2CKPS0 bit 0
TOUTPS3
Unimplemented: Read as `0' TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 =1:1 Postscaler 0001 =1:2 Postscaler 0010 =1:3 Postscaler 0011 =1:4 Postscaler 0100 =1:5 Postscaler 0101 =1:6 Postscaler 0110 =1:7 Postscaler 0111 =1:8 Postscaler 1000 =1:9 Postscaler 1001 =1:10 Postscaler 1010 =1:11 Postscaler 1011 =1:12 Postscaler 1100 =1:13 Postscaler 1101 =1:14 Postscaler 1110 =1:15 Postscaler 1111 =1:16 Postscaler TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 =Prescaler is 1 01 =Prescaler is 4 1x =Prescaler is 16
bit 2
bit 1-0
TABLE 8-1:
Name INTCON PIE1 PIR1 PR2(1) TMR2(1) T2CON(1) Legend: Note 1: Bit 7 GIE -- --
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Bit 6 PEIE ADIE(1) ADIF(1) Bit 5 T0IE CCP1IE(1) CCP1IF(1) Bit 4 INTE -- -- Bit 3 GPIE CMIE CMIF Bit 2 T0IF -- -- Bit 1 INTF TMR2IE(1) TMR2IF(1) Bit 0 GPIF TMR1IE TMR1IF Value on POR, BOR 0000 0000 -00- 0-00 -00- 0-00 1111 1111 0000 0000 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 Value on all other Resets 0000 0000 -00- 0-00 -00- 0-00 1111 1111 0000 0000 -000 0000
Timer2 Module Period Register Holding Register for the 8-bit TMR2 Register -- TOUTPS3 TOUTPS2 TOUTPS1
x = unknown, u = unchanged, - = unimplemented read as `0'. Shaded cells are not used for Timer2 module. For PIC12F615/617/HV615 only.
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9.0 COMPARATOR MODULE
The comparator can be used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparator is a very useful mixed signal building block because it provides analog functionality independent of the program execution. The Analog Comparator module includes the following features: * * * * * * * * * * Programmable input section Comparator output is available internally/externally Programmable output polarity Interrupt-on-change Wake-up from Sleep PWM shutdown Timer1 gate (count enable) Output synchronization to Timer1 clock input Programmable voltage reference User-enable Comparator Hysteresis than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level.
FIGURE 9-1:SINGLE COMPARATOR
VIN+ VIN+ - Output
VINVIN+
Output
9.1
Comparator Overview
Note:
The comparator is shown in Figure 9-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less
The black areas of the output of the comparator represents the uncertainty due to input offsets and response time.
FIGURE 9-2:
COMPARATOR SIMPLIFIED BLOCK DIAGRAM
CMPOL D Q1 CMCH D Q3*RD_CMCON0 CMON(1) Q EN Q To Data Bus RD_CMCON0 Set CMIF EN CL
GP1/CIN0-
0 Reset MUX CMVINCMVIN+
To PWM Auto-Shutdown CMSYNC CMPOL D Q CMOE COUT(4)
GP4/CIN1-
1
CMR
0 MUX 1
GP0/CIN+
FixedRef CVREF CMVREN 0 CMVREF MUX 1
0 MUX 1
From Timer1 Clock SYNCCMOUT To Timer1 Gate
Note 1: 2: 3: 4:
When CMON = 0, the comparator will produce a `0' output to the XOR Gate. Q1 and Q3 are phases of the four-phase system clock (FOSC). Q1 is held high during Sleep mode. Output shown for reference only. See I/O port pin diagram for more details.
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9.2 Analog Input Connection Considerations
Note 1: When reading a GPIO register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified.
A simplified circuit for an analog input is shown in Figure 9-3. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced.
FIGURE 9-3:
ANALOG INPUT MODEL
VDD
RS < 10K AIN VA CPIN 5 pF
VT 0.6V
RIC To Comparator
VT 0.6V
ILEAKAGE 500 nA
VSS Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Source Impedance RS VA = Analog Voltage = Threshold Voltage VT
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9.3 Comparator Control
9.3.5 COMPARATOR OUTPUT POLARITY
The comparator has two control and Configuration registers: CMCON0 and CMCON1. The CMCON1 register is used for controlling the interaction with Timer1 and simultaneously reading the comparator output. The CMCON0 register (Register 9-1) contain the control and Status bits for the following: * * * * * Enable Input selection Reference selection Output selection Output polarity Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CMPOL bit of the CMCON0 register. Clearing CMPOL results in a non-inverted output. A complete table showing the output state versus input conditions and the polarity bit is shown in Table 9-1.
TABLE 9-1:
OUTPUT STATE VS. INPUT CONDITIONS
CMPOL 0 0 1 1 COUT 0 1 1 0
Input Conditions CMVIN- > CMVIN+ CMVIN- < CMVIN+ CMVIN- > CMVIN+ CMVIN- < CMVIN+ Note:
9.3.1
COMPARATOR ENABLE
Setting the CMON bit of the CMCON0 register enables the comparator for operation. Clearing the CMON bit disables the comparator for minimum current consumption.
COUT refers to both the register bit and output pin.
9.3.2
COMPARATOR INPUT SELECTION
9.4
Comparator Response Time
The CMCH bit of the CMCON0 register directs one of four analog input pins to the comparator inverting input. Note: To use CIN+ and CIN- pins as analog inputs, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers.
9.3.3
COMPARATOR REFERENCE SELECTION
The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See Section 16.0 "Electrical Specifications" for more details.
Setting the CMR bit of the CMxCON0 register directs an internal voltage reference or an analog input pin to the non-inverting input of the comparator. See Section 9.10 "Comparator Voltage Reference" for more information on the internal voltage reference module.
9.3.4
COMPARATOR OUTPUT SELECTION
The output of the comparator can be monitored by reading either the COUT bit of the CMCON0 register. In order to make the output available for an external connection, the following conditions must be true: * CMOE bit of the CMxCON0 register must be set * Corresponding TRIS bit must be cleared * CMON bit of the CMCON0 register must be set. Note 1: The CMOE bit overrides the PORT data latch. Setting the CMON has no impact on the port override. 2: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched.
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9.5 Comparator Interrupt Operation
FIGURE 9-4:
The comparator interrupt flag can be set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusiveor gate (see Figure 9-4 and Figure 9-5). One latch is updated with the comparator output level when the CMCON0 register is read. This latch retains the value until the next read of the CMCON0 register or the occurrence of a Reset. The other latch of the mismatch circuit is updated on every Q1 system clock. A mismatch condition will occur when a comparator output change is clocked through the second latch on the Q1 clock cycle. At this point the two mismatch latches have opposite output levels which is detected by the exclusive-or gate and fed to the interrupt circuitry. The mismatch condition persists until either the CMCON0 register is read or the comparator output returns to the previous state. Note 1: A write operation to the CMCON0 register will also clear the mismatch condition because all writes include a read operation at the beginning of the write cycle. 2: Comparator interrupts will operate correctly regardless of the state of CMOE. The comparator interrupt is set by the mismatch edge and not the mismatch level. This means that the interrupt flag can be reset without the additional step of reading or writing the CMCON0 register to clear the mismatch registers. When the mismatch registers are cleared, an interrupt will occur upon the comparator's return to the previous state, otherwise no interrupt will be generated. Software will need to maintain information about the status of the comparator output, as read from the CMCON1 register, to determine the actual change that has occurred. The CMIF bit of the PIR1 register is the Comparator Interrupt flag. This bit must be reset in software by clearing it to `0'. Since it is also possible to write a '1' to this register, an interrupt can be generated. The CMIE bit of the PIE1 register and the PEIE and GIE bits of the INTCON register must all be set to enable comparator interrupts. If any of these bits are cleared, the interrupt is not enabled, although the CMIF bit of the PIR1 register will still be set if an interrupt condition occurs.
COMPARATOR INTERRUPT TIMING W/O CMCON0 READ
Q1 Q3 CIN+ COUT Set CMIF (edge) CMIF reset by software TRT
FIGURE 9-5:
COMPARATOR INTERRUPT TIMING WITH CMCON0 READ
Q1 Q3 CIN+ COUT Set CMIF (edge) CMIF cleared by CMCON0 read reset by software TRT
Note 1: If a change in the CMCON0 register (COUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF of the PIR1 register interrupt flag may not get set. 2: When a comparator is first enabled, bias circuitry in the comparator module may cause an invalid output from the comparator until the bias circuitry is stable. Allow about 1 s for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts.
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9.6 Operation During Sleep
The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in the Section 16.0 "Electrical Specifications". If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. The comparator is turned off by clearing the CMON bit of the CMCON0 register. A change to the comparator output can wake-up the device from Sleep. To enable the comparator to wake the device from Sleep, the CMIE bit of the PIE1 register and the PEIE bit of the INTCON register must be set. The instruction following the SLEEP instruction always executes following a wake from Sleep. If the GIE bit of the INTCON register is also set, the device will then execute the Interrupt Service Routine.
9.7
Effects of a Reset
A device Reset forces the CMCON1 register to its Reset state. This sets the comparator and the voltage reference to the OFF state.
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REGISTER 9-1:
R/W-0 CMON bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CMCON0: COMPARATOR CONTROL REGISTER 0
R-0 COUT R/W-0 CMOE R/W-0 CMPOL U-0 -- R/W-0 CMR U-0 -- R/W-0 CMCH bit 0
CMON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled COUT: Comparator Output bit If C1POL = 1 (inverted polarity): COUT = 0 when CMVIN+ > CMVINCOUT = 1 when CMVIN+ < CMVINIf C1POL = 0 (non-inverted polarity): COUT = 1 when CMVIN+ > CMVINCOUT = 0 when CMVIN+ < CMVINCMOE: Comparator Output Enable bit 1 = COUT is present on the COUT pin(1) 0 = COUT is internal only CMPOL: Comparator Output Polarity Select bit 1 = COUT logic is inverted 0 = COUT logic is not inverted Unimplemented: Read as `0' CMR: Comparator Reference Select bit (non-inverting input) 1 = CMVIN+ connects to CMVREF output 0 = CMVIN+ connects to CIN+ pin Unimplemented: Read as `0' CMCH: Comparator C1 Channel Select bit 0 = CMVIN- pin of the Comparator connects to CIN01 = CMVIN- pin of the Comparator connects to CIN1Comparator output requires the following three conditions: CMOE = 1, CMON = 1 and corresponding port TRIS bit = 0.
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1 bit 0
Note 1:
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9.8 Comparator Gating Timer1 9.9
This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CMCON1 register will enable Timer1 to increment based on the output of the comparator. This requires that Timer1 is on and gating is enabled. See Section 7.0 "Timer1 Module with Gate Control" for details. It is recommended to synchronize the comparator with Timer1 by setting the CMSYNC bit when the comparator is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if the comparator changes during an increment.
Synchronizing Comparator Output to Timer1
The comparator output can be synchronized with Timer1 by setting the CMSYNC bit of the CMCON1 register. When enabled, the comparator output is latched on the falling edge of the Timer1 clock source. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure 92) and the Timer1 Block Diagram (Figure 7-1) for more information.
REGISTER 9-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4
CMCON1: COMPARATOR CONTROL REGISTER 1
U-0 -- U-0 -- R/W-0 T1ACS R/W-0 CMHYS U-0 -- R/W-1 T1GSS R/W-0 CMSYNC bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' T1ACS: Timer1 Alternate Clock Select bit 1 = Timer 1 Clock Source is System Clock (FOSC) 0 = Timer 1 Clock Source is Instruction Clock (FOSC\4) CMHYS: Comparator Hysteresis Select bit 1 = Comparator Hysteresis enabled 0 = Comparator Hysteresis disabled Unimplemented: Read as `0' T1GSS: Timer1 Gate Source Select bit(1) 1 = Timer 1 Gate Source is T1G pin (pin should be configured as digital input) 0 = Timer 1 Gate Source is comparator output CMSYNC: Comparator Output Synchronization bit(2) 1 = Output is synchronized with falling edge of Timer1 clock 0 = Output is asynchronous Refer to Section 7.6 "Timer1 Gate". Refer to Figure 9-2.
bit 3
bit 2 bit 1
bit 0
Note 1: 2:
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9.10 Comparator Voltage Reference
9.10.3 OUTPUT CLAMPED TO VSS
The Comparator Voltage Reference module provides an internally generated voltage reference for the comparators. The following features are available: * * * * * Independent from Comparator operation 16-level voltage range Output clamped to VSS Ratiometric with VDD Fixed Reference (0.6) The CVREF output voltage can be set to Vss with no power consumption by configuring VRCON as follows: * FVREN = 0 This allows the comparator to detect a zero-crossing while not consuming additional CVREF module current.
9.10.4
OUTPUT RATIOMETRIC TO VDD
The VRCON register (Register 9-3) controls the Voltage Reference module shown in Register 9-6.
9.10.1
INDEPENDENT OPERATION
The comparator voltage reference is VDD derived and therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the Comparator Voltage Reference can be found in Section 16.0 "Electrical Specifications".
The comparator voltage reference is independent of the comparator configuration. Setting the VREN bit of the VRCON register will enable the voltage reference.
9.10.5
FIXED VOLTAGE REFERENCE
9.10.2
OUTPUT VOLTAGE SELECTION
The CVREF voltage reference has 2 ranges with 16 voltage levels in each range. Range selection is controlled by the VRR bit of the VRCON register. The 16 levels are set with the VR<3:0> bits of the VRCON register.
The fixed voltage reference is independent of VDD, with a nominal output voltage of 0.6V. This reference can be enabled by setting the FVREN bit of the VRCON register to `1'. This reference is always enabled when the HFINTOSC oscillator is active.
9.10.6
FIXED VOLTAGE REFERENCE STABILIZATION PERIOD
The CVREF output voltage is determined by the
following equations:
EQUATION 9-1:
CVREF OUTPUT VOLTAGE
VRR = 1 (low range): CVREF = (VR<3:0>/24) VDD VRR = 0 (high range): CVREF = (VDD/4) + (VR<3:0> VDD/32) The full range of VSS to VDD cannot be realized due to the construction of the module. See Figure 9-6.
When the Fixed Voltage Reference module is enabled, it will require some time for the reference and its amplifier circuits to stabilize. The user program must include a small delay routine to allow the module to settle. See Section 16.0 "Electrical Specifications" for the minimum delay requirement.
9.10.7
VOLTAGE REFERENCE SELECTION
Multiplexers on the output of the Voltage Reference module enable selection of either the CVREF or fixed voltage reference for use by the comparators. Setting the CMVREN bit of the VRCON register enables current to flow in the CVREF voltage divider and selects the CVREF voltage for use by the Comparator. Clearing the CMVREN bit selects the fixed voltage for use by the Comparator. When the CMVREN bit is cleared, current flow in the CVREF voltage divider is disabled minimizing the power drain of the voltage reference peripheral.
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FIGURE 9-6: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages 8R VDD 8R Analog MUX 15 VRR R R R R
CMVREN CVREF(1) To Comparators and ADC Module
0 VR<3:0>(1) 4
FVREN Sleep HFINTOSC enable FixedRef To Comparators and ADC Module 0.6V EN Fixed Voltage Reference
Note 1:
Care should be taken to ensure CVREF remains within the comparator common mode input range. See Section 16.0 "Electrical Specifications" for more detail.
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REGISTER 9-3:
R/W-0 CMVREN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
VRCON: VOLTAGE REFERENCE CONTROL REGISTER
U-0 -- R/W-0 VRR R/W-0 FVREN R/W-0 VR3 R/W-0 VR2 R/W-0 VR1 R/W-0 VR0 bit 0
CMVREN: Comparator Voltage Reference Enable bit(1, 2) 1 = CVREF circuit powered on and routed to CVREF input of the Comparator 0 = 0.6 Volt constant reference routed to CVREF input of the Comparator Unimplemented: Read as `0' VRR: CVREF Range Selection bit 1 = Low range 0 = High range FVREN: 0.6V Reference Enable bit(2) 1 = Enabled 0 = Disabled VR<3:0>: Comparator Voltage Reference CVREF Value Selection bits (0 VR<3:0> 15) When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD When CMVREN is low, the CVREF circuit is powered down and does not contribute to IDD current. When CMVREN is low and the FVREN bit is low, the CVREF signal should provide Vss to the comparator.
bit 6 bit 5
bit 4
bit 3-0
Note 1: 2:
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9.11 Comparator Hysteresis
Each comparator has built-in hysteresis that is user enabled by setting the CMHYS bit of the CMCON1 register. The hysteresis feature can help filter noise and reduce multiple comparator output transitions when the output is changing state. Figure 9-7 shows the relationship between the analog input levels and digital output of a comparator with and without hysteresis. The output of the comparator changes from a low state to a high state only when the analog voltage at VIN+ rises above the upper hysteresis threshold (VH+). The output of the comparator changes from a high state to a low state only when the analog voltage at VIN+ falls below the lower hysteresis threshold (VH-).
FIGURE 9-7:
COMPARATOR HYSTERESIS
VIN+ VIN-
+ Output -
V+
VH+ VINVHVIN+
Output (Without Hysteresis)
Output (With Hysteresis)
Note:
The black areas of the comparator output represents the uncertainty due to input offsets and response time.
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TABLE 9-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES
Bit 7 -- CMON -- GIE -- -- -- -- CMVREN Bit 6 ADCS2(1) COUT -- PEIE ADIE(1) ADIF(1) -- -- -- Bit 5 ADCS1(1) CMOE -- T0IE CCP1IE(1) CCP1IF(1) GP5 TRISIO5 VRR Bit 4 ADCS0(1) CMPOL T1ACS INTE -- -- GP4 TRISIO4 FVREN Bit 3 ANS3 -- CMHYS GPIE CMIE CMIF GP3 TRISIO3 VR3 Bit 2 ANS2(1) CMR -- T0IF -- -- GP2 TRISIO2 VR2 Bit 1 ANS1 -- T1GSS INTF TMR2IE(1) TMR2IF(1) GP1 TRISIO1 VR1 Bit 0 ANS0 CMCH CMSYNC GPIF TMR1IE TMR1IF GP0 TRISIO0 VR0 Value on POR, BOR -000 1111 0000 -000 0000 0000 0000 000x -00- 0-00 -00- 0-00 --xx xxxx --11 1111 0-00 0000 Value on all other Resets -000 1111 0000 -000 0000 0000 0000 000x -00- 0-00 -00- 0-00 --uu uuuu --11 1111 0-00 0000
Name ANSEL CMCON0 CMCON1 INTCON PIE1 PIR1 GPIO TRISIO VRCON Legend:
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used for comparator.
For PIC12F615/617/HV615 only.
Note 1:
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10.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE (PIC12F615/617/HV615 ONLY)
Note: The ADRESL and ADRESH registers are Read Only.
The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESL and ADRESH). The ADC voltage reference is software selectable to either VDD or a voltage applied to the external reference pins. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. Figure 10-1 shows the block diagram of the ADC.
FIGURE 10-1:
ADC BLOCK DIAGRAM
VDD
VCFG = 0
VREF
VCFG = 1
GP0/AN0 GP1/AN1/VREF GP2/AN2 GP4/AN3 CVREF 0.6V Reference 1.2V Reference
000 001 010 011 100 101 110 GO/DONE ADFM ADON CHS VSS ADRESH A/D 10 0 = Left Justify 1 = Right Justify 10 ADRESL
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10.1 ADC Configuration
10.1.3
ADC VOLTAGE REFERENCE
When configuring and using the ADC the following functions must be considered: * * * * * * Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting
The VCFG bit of the ADCON0 register provides control of the positive voltage reference. The positive voltage reference can be either VDD or an external voltage source. The negative voltage reference is always connected to the ground reference.
10.1.4
CONVERSION CLOCK
The source of the conversion clock is software selectable via the ADCS bits of the ANSEL register. There are seven possible clock options: * * * * * * * FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal oscillator)
10.1.1
PORT CONFIGURATION
The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. See the corresponding port section for more information. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current.
10.1.2
CHANNEL SELECTION
The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11 TAD periods as shown in Figure 10-3. For correct conversion, the appropriate TAD specification must be met. See A/D conversion requirements in Section 16.0 "Electrical Specifications" for more information. Table 10-1 gives examples of appropriate ADC clock selections. Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result.
The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 10.2 "ADC Operation" for more information.
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TABLE 10-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)
Device Frequency (FOSC) 20 MHz 100 ns 400 ns 800 ns
(2)
ADC Clock Period (TAD) ADC Clock Source FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC Legend: Note 1: 2: 3: 4: ADCS<2:0> 000 100 001 101 010 110 x11
8 MHz 250 ns 1.0 s
(2)
4 MHz 500 ns
(2)
1 MHz 2.0 s 4.0 s 8.0 s(3) 16.0 s(3) 32.0 s(3) 64.0 s(3) 2-6 s(1,4)
200 ns(2)
(2) (2)
500 ns(2)
(2)
1.0 s(2) 2.0 s 4.0 s 8.0 s(3) 16.0 s
(3)
2.0 s 4.0 s 8.0 s
(3)
1.6 s 3.2 s 2-6 s(1,4)
2-6 s(1,4)
2-6 s(1,4)
Shaded cells are outside of recommended range. The FRC source has a typical TAD time of 4 s for VDD > 3.0V. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep.
FIGURE 10-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion Starts Holding Capacitor is Disconnected from Analog Input (typically 100 ns) Set GO/DONE bit ADRESH and ADRESL registers are loaded, GO bit is cleared, ADIF bit is set, Holding capacitor is connected to analog input
10.1.5
INTERRUPTS
The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC interrupt flag is the ADIF bit in the PIR1 register. The ADC interrupt enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled.
This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the Interrupt Service Routine. Please see Section 10.1.5 "Interrupts" for more information.
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10.1.6 RESULT FORMATTING
The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format. Figure 10-4 shows the two output formats.
FIGURE 10-3:
10-BIT A/D CONVERSION RESULT FORMAT
ADRESH ADRESL LSB bit 0 10-bit A/D Result bit 7 bit 0 Unimplemented: Read as `0' LSB bit 0 bit 7 10-bit A/D Result bit 0
(ADFM = 0)
MSB bit 7
(ADFM = 1) bit 7 Unimplemented: Read as `0'
MSB
10.2
10.2.1
ADC Operation
STARTING A CONVERSION
10.2.4
ADC OPERATION DURING SLEEP
To enable the ADC module, the ADON bit of the ADCON0 register must be set to a `1'. Setting the GO/ DONE bit of the ADCON0 register to a `1' will start the Analog-to-Digital conversion. Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 10.2.6 "A/D Conversion Procedure".
The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set.
10.2.2
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will: * Clear the GO/DONE bit * Set the ADIF flag bit * Update the ADRESH:ADRESL registers with new conversion result
10.2.5
SPECIAL EVENT TRIGGER
10.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRESH:ADRESL registers will not be updated with the partially complete Analog-to-Digital conversion sample. Instead, the ADRESH:ADRESL register pair will retain the value of the previous conversion. Additionally, a 2 TAD delay is required before another acquisition can be initiated. Following this delay, an input acquisition is automatically started on the selected channel. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated.
The ECCP Special Event Trigger allows periodic ADC measurements without software intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to zero. Using the Special Event Trigger does not assure proper ADC timing. It is the user's responsibility to ensure that the ADC timing requirements are met. See Section 11.0 "Enhanced Capture/Compare/ PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only)" for more information.
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10.2.6 A/D CONVERSION PROCEDURE EXAMPLE 10-1: A/D CONVERSION
This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. Configure Port: * Disable pin output driver (See TRIS register) * Configure pin as analog Configure the ADC module: * Select ADC conversion clock * Configure voltage reference * Select ADC input channel * Select result format * Turn on ADC module Configure ADC interrupt (optional): * Clear ADC interrupt flag * Enable ADC interrupt * Enable peripheral interrupt * Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: * Polling the GO/DONE bit * Waiting for the ADC interrupt (interrupts enabled) Read ADC Result Clear the ADC interrupt flag (required if interrupt is enabled).
;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and GP0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL TRISIO ; BSF TRISIO,0 ;Set GP0 to input BANKSEL ANSEL ; MOVLW B'01110001' ;ADC Frc clock, IORWF ANSEL ; and GP0 as analog BANKSEL ADCON0 ; MOVLW B'10000001' ;Right justify, MOVWF ADCON0 ;Vdd Vref, AN0, On CALL SampleTime ;Acquisiton delay BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;Store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space
2.
3.
4. 5. 6.
7. 8.
Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: See Section 10.3 "A/D Acquisition Requirements".
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10.2.7 ADC REGISTER DEFINITIONS
The following registers are used to control the operation of the ADC.
REGISTER 10-1:
R/W-0 ADFM bit 7 Legend: R = Readable bit -n = Value at POR bit 7
ADCON0: A/D CONTROL REGISTER 0
R/W-0 VCFG U-0 -- R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified VCFG: Voltage Reference bit 1 = VREF pin 0 = VDD Unimplemented: Read as `0' CHS<2:0>: Analog Channel Select bits 000 = Channel 00 (AN0) 001 = Channel 01 (AN1) 010 = Channel 02 (AN2) 011 = Channel 03 (AN3) 100 = CVREF 101 = 0.6V Reference 110 = 1.2V Reference 111 = Reserved. Do not use. GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current When the CHS<2:0> bits change to select the 1.2V or 0.6V reference, the reference output voltage will have a transient. If the Comparator module uses this 0.6V reference voltage, the comparator output may momentarily change state due to the transient.
bit 6
bit 5 bit 4-2
bit 1
bit 0
Note 1:
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REGISTER 10-2:
R-x ADRES9 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 (READ-ONLY)
R-x R-x ADRES7 R-x ADRES6 R-x ADRES5 R-x ADRES4 R-x ADRES3 R-x ADRES2 bit 0
ADRES8
ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result
REGISTER 10-3:
R-x ADRES1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 (READ-ONLY)
R-x U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
ADRES0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result Unimplemented: Read as `0'
REGISTER 10-4:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 bit 1-0
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 (READ-ONLY)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R-x ADRES9 R-x ADRES8 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' ADRES<9:8>: ADC Result Register bits Upper 2 bits of 10-bit conversion result
REGISTER 10-5:
R-x ADRES7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 (READ-ONLY)
R-x R-x ADRES5 R-x ADRES4 R-x ADRES3 R-x ADRES2 R-x ADRES1 R-x ADRES0 bit 0
ADRES6
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result
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10.3 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 10-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 10-4. The maximum recommended impedance for analog sources is 10 k. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 10-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution.
EQUATION 10-1: Assumptions:
ACQUISITION TIME EXAMPLE Temperature = 50C and external impedance of 10k 5.0V VDD
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF = 2s + TC + Temperature - 25C 0.05s/C The value for TC can be approximated with the following equations:
1 VAPPLIED 1 - ----------- = VCHOLD 2047
--------- RC VAPPLIED 1 - e = VCHOLD -------- 1 RC VAPPLIED 1 - e = VAPPLIED 1 - ----------- 2047 - Tc - TC
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
Solving for TC:
TC = - CHOLD RIC + RSS + RS ln(1/2047) = - 10pF 1k + 7k + 10k ln(0.0004885) = 1.37 s
Therefore: TACQ = 2s + 1.37s + 50C- 25C 0.05s/C = 4.67s
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.
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FIGURE 10-4: ANALOG INPUT MODEL
VDD Rs VA ANx CPIN 5 pF VT = 0.6V RIC 1k I LEAKAGE 500 nA Sampling Switch SS Rss
VT = 0.6V
CHOLD = 10 pF VSS/VREF-
Legend: CPIN = Input Capacitance = Threshold Voltage VT I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance SS = Sampling Switch CHOLD = Sample/Hold Capacitance
6V 5V VDD 4V 3V 2V
RSS
5 6 7 8 9 10 11 Sampling Switch (k)
FIGURE 10-5:
ADC TRANSFER FUNCTION
Full-Scale Range
3FFh 3FEh 3FDh ADC Output Code 3FCh 3FBh Full-Scale Transition 1 LSB ideal
004h 003h 002h 001h 000h 1 LSB ideal
Analog Input Voltage
VSS/VREF-
Zero-Scale Transition
VDD/VREF+
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TABLE 10-2:
Name ADCON0(1) ANSEL ADRESH GPIO INTCON PIE1 PIR1 TRISIO Legend: Note 1: 2:
(1,2)
SUMMARY OF ASSOCIATED ADC REGISTERS
Bit 6 VCFG ADCS2(1) Bit 5 -- ADCS1(1) Bit 4 CHS2 ADCS0(1) Bit 3 CHS1 ANS3 Bit 2 CHS0 ANS2(1) Bit 1 GO/DONE ANS1 Bit 0 ADON ANS0 Value on POR, BOR Value on all other Resets
Bit 7 ADFM --
00-0 0000 00-0 0000 -000 1111 -000 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
A/D Result Register High Byte -- GIE -- -- -- -- PEIE ADIE(1) ADIF(1) -- GP5 T0IE CCP1IE(1) CCP1IF(1) TRISIO5 GP4 INTE -- -- TRISIO4 GP3 GPIE CMIE CMIF TRISIO3 GP2 T0IF -- -- TRISIO2 GP1 INTF TMR2IE(1) TMR2IF(1) TRISIO1 GP0 GPIF TMR1IE TMR1IF
ADRESL(1,2) A/D Result Register Low Byte
--x0 x000 --x0 x000 0000 0000 0000 0000 -00- 0-00 -00- 0-00 -00- 0-00 -00- 0-00
TRISIO0 --11 1111 --11 1111
x = unknown, u = unchanged, -- = unimplemented read as `0'. Shaded cells are not used for ADC module. For PIC12F615/617/HV615 only. Read Only Register.
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11.0 ENHANCED CAPTURE/ COMPARE/PWM (WITH AUTOSHUTDOWN AND DEAD BAND) MODULE (PIC12F615/617/ HV615 ONLY)
event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle. Table 11-1 shows the timer resources required by the ECCP module.
The Enhanced Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event.The Compare mode allows the user to trigger an external
TABLE 11-1:
ECCP MODE - TIMER RESOURCES REQUIRED
Timer Resource Timer1 Timer1 Timer2
ECCP Mode Capture Compare PWM
REGISTER 11-1:
R/W-0 P1M bit 7 Legend: R = Readable bit -n = Value at POR bit 7
CCP1CON: ENHANCED CCP1 CONTROL REGISTER
U-0 --
R/W-0 DC1B1 R/W-0 DC1B0 R/W-0 CCP1M3 R/W-0 CCP1M2 R/W-0 CCP1M1 R/W-0 CCP1M0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
P1M: PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: x = P1A assigned as Capture/Compare input; P1B assigned as port pins If CCP1M<3:2> = 11: 0 = Single output; P1A modulated; P1B assigned as port pins 1 = Half-Bridge output; P1A, P1B modulated with dead-band control
bit 6
bit 5-4
Unimplemented: Read as `0'
DC1B<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. CCP1M<3:0>: ECCP Mode Select bits 0000 =Capture/Compare/PWM off (resets ECCP module) 0001 =Unused (reserved) 0010 =Compare mode, toggle output on match (CCP1IF bit is set) 0011 =Unused (reserved) 0100 =Capture mode, every falling edge 0101 =Capture mode, every rising edge 0110 =Capture mode, every 4th rising edge 0111 =Capture mode, every 16th rising edge 1000 =Compare mode, set output on match (CCP1IF bit is set) 1001 =Compare mode, clear output on match (CCP1IF bit is set) 1010 =Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 =Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 or TMR2 and starts an A/D conversion, if the ADC module is enabled) 1100 =PWM mode; P1A active-high; P1B active-high 1101 =PWM mode; P1A active-high; P1B active-low 1110 =PWM mode; P1A active-low; P1B active-high 1111 =PWM mode; P1A active-low; P1B active-low
bit 3-0
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11.1 Capture Mode
11.1.2 TIMER1 MODE SELECTION
In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work.
11.1.3
SOFTWARE INTERRUPT
When a capture is made, the Interrupt Request Flag bit CCP1IF of the PIR1 register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPR1H, CCPR1L register pair is read, the old captured value is overwritten by the new captured value (see Figure 11-1).
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCP1IE interrupt enable bit of the PIE1 register clear to avoid false interrupts. Additionally, the user should clear the CCP1IF interrupt flag bit of the PIR1 register following any change in operating mode.
11.1.4
CCP PRESCALER
11.1.1
CCP1 PIN CONFIGURATION
In Capture mode, the CCP1 pin should be configured as an input by setting the associated TRIS control bit. Note: If the CCP1 pin is configured as an output, a write to the port can cause a capture condition.
There are four prescaler settings specified by the CCP1M<3:0> bits of the CCP1CON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCP1CON register before changing the prescaler (see Example 11-1).
FIGURE 11-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set Flag bit CCP1IF (PIR1 register)
EXAMPLE 11-1:
BANKSEL CCP1CON CLRF MOVLW
CHANGING BETWEEN CAPTURE PRESCALERS
Prescaler 1, 4, 16 CCP1 pin
CCPR1H and Edge Detect Capture Enable TMR1H
CCPR1L
MOVWF
TMR1L
;Set Bank bits to point ;to CCP1CON CCP1CON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ; the new prescaler ; move value and CCP ON CCP1CON ;Load CCP1CON with this ; value
CCP1CON<3:0> System Clock (FOSC)
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TABLE 11-2:
Name CCP1CON CCPR1L CCPR1H INTCON PIE1 PIR1 T1CON TMR1L TMR1H TRISIO
SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
Bit 6 -- Bit 5 DC1B1 Bit 4 DC1B0 Bit 3 CCP1M3 Bit 2 CCP1M2 Bit 1 CCP1M1 Bit 0 Value on POR, BOR Value on all other Resets
Bit 7 P1M
CCP1M0 0-00 0000 0-00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register 1 Low Byte Capture/Compare/PWM Register 1 High Byte GIE -- -- T1GINV PEIE ADIE(1) ADIF(1) T0IE CCP1IE(1) CCP1IF(1) INTE -- -- GPIE CMIE CMIF T0IF -- -- INTF TMR2IE(1) TMR2IF(1) GPIF TMR1IE TMR1IF
0000 0000 0000 0000 -00- 0-00 -00- 0-00 -00- 0-00 -00- 0-00
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TRISIO0 --11 1111 --11 1111
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register -- -- TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1
Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Capture. Note 1: For PIC12F615/617/HV615 only.
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11.2 Compare Mode
11.2.2 TIMER1 MODE SELECTION
In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 module may: * * * * * Toggle the CCP1 output. Set the CCP1 output. Clear the CCP1 output. Generate a Special Event Trigger. Generate a Software Interrupt. In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode.
11.2.3
SOFTWARE INTERRUPT MODE
The action on the pin is based on the value of the CCP1M<3:0> control bits of the CCP1CON register. All Compare modes can generate an interrupt.
When Generate Software Interrupt mode is chosen (CCP1M<3:0> = 1010), the CCP1 module does not assert control of the CCP1 pin (see the CCP1CON register).
11.2.4
SPECIAL EVENT TRIGGER
FIGURE 11-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
CCP1CON<3:0> Mode Select Set CCP1IF Interrupt Flag (PIR1) 4 CCPR1H CCPR1L
When Special Event Trigger mode is chosen (CCP1M<3:0> = 1011), the CCP1 module does the following: * Resets Timer1 * Starts an ADC conversion if ADC is enabled The CCP1 module does not assert control of the CCP1 pin in this mode (see the CCP1CON register). The Special Event Trigger output of the CCP occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPR1H, CCPR1L register pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. This allows the CCPR1H, CCPR1L register pair to effectively provide a 16-bit programmable period register for Timer1. Note 1: The Special Event Trigger from the CCP module does not set interrupt flag bit TMRxIF of the PIR1 register. 2: Removing the match condition by changing the contents of the CCPR1H and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring.
CCP1 Pin Q S R TRIS Output Enable
Output Logic
Match
Comparator TMR1H TMR1L
Special Event Trigger Special Event Trigger will: * Clear TMR1H and TMR1L registers. * NOT set interrupt flag bit TMR1IF of the PIR1 register. * Set the GO/DONE bit to start the ADC conversion.
11.2.1
CCP1 PIN CONFIGURATION
The user must configure the CCP1 pin as an output by clearing the associated TRIS bit. Note: Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the PORT I/O data latch.
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TABLE 11-3:
Name CCP1CON CCPR1L CCPR1H INTCON PIE1 PIR1 T1CON TMR1L TMR1H TMR2 TRISIO
SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
Bit 6 -- Bit 5 DC1B1 Bit 4 DC1B0 Bit 3 CCP1M3 Bit 2 CCP1M2 Bit 1 CCP1M1 Bit 0 Value on POR, BOR Value on all other Resets
Bit 7 P1M
CCP1M0 0-00 0000 0-00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register 1 Low Byte Capture/Compare/PWM Register 1 High Byte GIE -- -- T1GINV PEIE ADIE(1) ADIF(1) T0IE CCP1IE(1) CCP1IF(1) INTE -- -- GPIE CMIE CMIF T0IF -- -- INTF TMR2IE(1) TMR2IF(1) TMR1CS GPIF TMR1IE TMR1IF
0000 0000 0000 0000 -00- 0-00 -00- 0-00 -00- 0-00 -00- 0-00
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1ON 0000 0000 uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 0000 0000 TRISIO0 --11 1111 --11 1111
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register Timer2 Module Register -- -- TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1
Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Compare. Note 1: For PIC12F615/617/HV615 only.
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11.3 PWM Mode
The PWM mode generates a Pulse-Width Modulated signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: * * * * PR2 T2CON CCPR1L CCP1CON The PWM output (Figure 11-4) has a time base (period) and a time that the output stays high (duty cycle).
FIGURE 11-4:
Period Pulse Width
CCP PWM OUTPUT
TMR2 = PR2 TMR2 = CCPRxL:CCPxCON<5:4>
In Pulse-Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the CCP1 pin. Since the CCP1 pin is multiplexed with the PORT data latch, the TRIS for that pin must be cleared to enable the CCP1 pin output driver. Note: Clearing the CCP1CON register will relinquish CCP1 control of the CCP1 pin.
TMR2 = 0
Figure 11-3 shows a simplified block diagram of PWM operation. Figure 11-4 shows a typical waveform of the PWM signal. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 11.3.7 "Setup for PWM Operation".
FIGURE 11-3:
SIMPLIFIED PWM BLOCK DIAGRAM
CCP1CON<5:4>
Duty Cycle Registers CCPR1L
CCPR1H(2) (Slave) CCP1 Comparator
(1)
R S
Q
TMR2
TRIS Comparator Clear Timer2, toggle CCP1 pin and latch duty cycle
PR2
Note 1:
2:
The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. In PWM mode, CCPR1H is a read-only register.
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11.3.1 PWM PERIOD EQUATION 11-2: PULSE WIDTH
The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 11-1. Pulse Width = CCPR1L:CCP1CON<5:4> TOSC (TMR2 Prescale Value)
EQUATION 11-1:
PWM PERIOD EQUATION 11-3: DUTY CYCLE RATIO
PWM Period = PR2 + 1 4 TOSC (TMR2 Prescale Value) When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) * The PWM duty cycle is latched from CCPR1L into CCPR1H. Note: The Timer2 postscaler (see Section 8.1 "Timer2 Operation") is not used in the determination of the PWM frequency.
CCPR1L:CCP1CON<5:4> Duty Cycle Ratio = ---------------------------------------------------------------------4 PR2 + 1 The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPR1H and 2-bit latch, then the CCP1 pin is cleared (see Figure 113).
11.3.2
PWM DUTY CYCLE
11.3.3
PWM RESOLUTION
The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPR1L register and DC1B<1:0> bits of the CCP1CON register. The CCPR1L contains the eight MSbs and the DC1B<1:0> bits of the CCP1CON register contain the two LSbs. CCPR1L and DC1B<1:0> bits of the CCP1CON register can be written to at any time. The duty cycle value is not latched into CCPR1H until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPR1H register is read-only. Equation 11-2 is used to calculate the PWM pulse width. Equation 11-3 is used to calculate the PWM duty cycle ratio.
The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 11-4.
EQUATION 11-4:
PWM RESOLUTION
log 4 PR2 + 1 Resolution = ----------------------------------------- bits log 2
Note:
If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged.
TABLE 11-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
1.22 kHz 16 0xFF 10 4.88 kHz 4 0xFF 10 19.53 kHz 1 0xFF 10 78.12 kHz 1 0x3F 8 156.3 kHz 1 0x1F 7 208.3 kHz 1 0x17 6.6
PWM Frequency Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits)
TABLE 11-5:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
1.22 kHz 16 0x65 8 4.90 kHz 4 0x65 8 19.61 kHz 1 0x65 8 76.92 kHz 1 0x19 6 153.85 kHz 1 0x0C 5 200.0 kHz 1 0x09 5
PWM Frequency Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits)
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11.3.4 OPERATION IN SLEEP MODE 11.3.7 SETUP FOR PWM OPERATION
In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. Disable the PWM pin (CCP1) output drivers by setting the associated TRIS bit. Set the PWM period by loading the PR2 register. Configure the CCP module for the PWM mode by loading the CCP1CON register with the appropriate values. Set the PWM duty cycle by loading the CCPR1L register and DC1B bits of the CCP1CON register. Configure and start Timer2: Clear the TMR2IF interrupt flag bit of the PIR1 register. Set the Timer2 prescale value by loading the T2CKPS bits of the T2CON register. Enable Timer2 by setting the TMR2ON bit of the T2CON register. Enable PWM output after a new PWM cycle has started: Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set). Enable the CCP1 pin output driver by clearing the associated TRIS bit.
11.3.5
CHANGES IN SYSTEM CLOCK FREQUENCY
The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 4.0 "Oscillator Module" for additional details.
4. 5. * * * 6. * *
11.3.6
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the CCP registers to their Reset states.
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11.4 PWM (Enhanced Mode)
The Enhanced PWM Mode can generate a PWM signal on up to four different output pins with up to 10-bits of resolution. It can do this through four different PWM output modes: * Single PWM * Half-Bridge PWM To select an Enhanced PWM mode, the P1M bits of the CCP1CON register must be set appropriately. The PWM outputs are multiplexed with I/O pins and are designated P1A and P1B. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately. Table 11-6 shows the pin assignments for each Enhanced PWM mode. Figure 11-5 shows an example of a simplified block diagram of the Enhanced PWM module. Note: To prevent the generation of an incomplete waveform when the PWM is first enabled, the ECCP module waits until the start of a new PWM period before generating a PWM signal.
FIGURE 11-5:
EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
CCP1<1:0> P1M<1:0> 2 CCP1M<3:0> 4 (APFCON<0>) P1ASEL 0 CCP1/P1A TRISIO2 1 CCP1/P1A* TRISIO5
Duty Cycle Registers CCPR1L
CCPR1H (Slave)
CCP1/P1A R Q
Comparator
Output Controller (APFCON<1>) P1BSEL 0
TMR2
(1) S
Comparator Clear Timer2, toggle PWM pin and latch duty cycle P1B
P1B TRISIO0
PR2
1 TRISIO4 PWM1CON
P1B*
Note
* 1:
Alternate pin function. The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base.
Note 1: The TRIS register value for each PWM output must be configured appropriately. 2: Clearing the CCP1CON register will relinquish ECCP control of all PWM output pins. 3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.
TABLE 11-6:
ECCP Mode Single Half-Bridge
EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
P1M<1:0> 00 10 CCP1/P1A Yes(1) Yes P1B Yes(1) Yes
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FIGURE 11-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
Signal 0 Pulse Width Period 00 (Single Output) P1A Modulated Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active Relationships: P1B Inactive * Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) * Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) P1C Inactive * Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 "Programmable Dead-Band Delay mode"). P1D Modulated Delay(1) PR2+1
P1M<1:0>
FIGURE 11-7:
P1M<1:0>
EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
Signal 0 Pulse Width Period PR2+1
00
(Single Output)
P1A Modulated P1A Modulated Delay(1) Delay(1)
10
(Half-Bridge)
P1B Modulated P1A Active
Relationships: P1B Inactive * Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) * Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) P1C Inactive * Delay = 4 * TOSC * (PWM1CON<6:0>) Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 "Programmable Dead-Band Delay mode"). P1D Modulated
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11.4.1 HALF-BRIDGE MODE
In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 11-8). This mode can be used for Half-Bridge applications, as shown in Figure 11-9, or for Full-Bridge applications, where four power switches are being modulated with two PWM signals. In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in HalfBridge power devices. The value of the PDC<6:0> bits of the PWM1CON register sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 11.4.6 "Programmable Dead-Band Delay mode" for more details of the dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure P1A and P1B as outputs.
FIGURE 11-8:
Period
EXAMPLE OF HALFBRIDGE PWM OUTPUT
Period
Pulse Width P1A(2) td P1B(2)
(1)
td
(1)
(1)
td = Dead-Band Delay Note 1: 2: At this time, the TMR2 register is equal to the PR2 register. Output signals are shown as active-high.
FIGURE 11-9:
EXAMPLE OF HALF-BRIDGE APPLICATIONS
Standard Half-Bridge Circuit ("Push-Pull") FET Driver P1A
+ Load
FET Driver P1B
+ -
Half-Bridge Output Driving a Full-Bridge Circuit V+
FET Driver P1A Load
FET Driver
FET Driver P1B
FET Driver
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11.4.2 START-UP CONSIDERATIONS
When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the highimpedance state. The external circuits must keep the power switch devices in the OFF state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s).
The CCP1M<1:0> bits of the CCP1CON register allow the user to choose whether the PWM output signals are active-high or active-low for each PWM output pin (P1A and P1B). The PWM output polarities must be selected before the PWM pin output drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are enable is not recommended since it may result in damage to the application circuits. The P1A and P1B output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to the application circuit. The Enhanced PWM modes must be enabled in the proper Output mode and complete a full PWM cycle before configuring the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins.
11.4.3
OPERATION DURING SLEEP
When the device is placed in sleep, the allocated timer will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state.
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11.4.4 ENHANCED PWM AUTOSHUTDOWN MODE
The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the ECCPASx bits of the ECCPAS register. A shutdown event may be generated by: * A logic `0' on the INT pin * Comparator * Setting the ECCPASE bit in firmware A shutdown condition is indicated by the ECCPASE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a `0', the PWM pins are operating normally. If the bit is a `1', the PWM outputs are in the shutdown state. Refer to Figure 1. When a shutdown event occurs, two things happen: The ECCPASE bit is set to `1'. The ECCPASE will remain set until cleared in firmware or an auto-restart occurs (see Section 11.4.5 "Auto-Restart Mode"). The enabled PWM pins are asynchronously placed in their shutdown states. The state of P1A is determined by the PSSAC bit. The state of P1B is determined by the PSSBD bit. The PSSAC and PSSBD bits are located in the ECCPAS register. Each pin may be placed into one of three states: * Drive logic `1' * Drive logic `0' * Tri-state (high-impedance)
FIGURE 11-10:
AUTO-SHUTDOWN BLOCK DIAGRAM
ECCPAS<2:0>
111 110 101 100 INT 011 010 From Comparator PSSAC<0> 001 000 PRSEN P1A_DRV 1 0
PSSAC<1> R From Data Bus Write to ECCPASE D S TRISx Q ECCPASE PSSBD<0> P1B_DRV P1A
1 0
PSSBD<1> TRISx P1B
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REGISTER 11-2:
R/W-0 ECCPASE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER
R/W-0 R/W-0 ECCPAS1 R/W-0 ECCPAS0 R/W-0 PSSAC1 R/W-0 PSSAC0 R/W-0 PSSBD1 R/W-0 PSSBD0 bit 0
ECCPAS2
ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECCP outputs are operating ECCPAS<2:0>: ECCP Auto-shutdown Source Select bits 000 =Auto-Shutdown is disabled 001 =Comparator output change 010 =Auto-Shutdown is disabled 011 =Comparator output change(1) 100 =VIL on INT pin 101 =VIL on INT pin or Comparator change 110 =VIL on INT pin(1) 111 =VIL on INT pin or Comparator change PSSAC<1:0>: Pin P1A Shutdown State Control bits 00 = Drive pin P1A to `0' 01 = Drive pin P1A to `1' 1x = Pin P1A tri-state PSSBD<1:0>: Pin P1B Shutdown State Control bits 00 = Drive pin P1B to `0' 01 = Drive pin P1B to `1' 1x = Pin P1B tri-state If CMSYNC is enabled, the shutdown will be delayed by Timer1.
bit 6-4
bit 3-2
bit 1-0
Note 1:
Note 1: The auto-shutdown condition is a levelbased signal, not an edge-based signal. As long as the level is present, the autoshutdown will persist. 2: Writing to the ECCPASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart) the PWM signal will always restart at the beginning of the next PWM period.
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PIC12F609/615/617/12HV609/615
FIGURE 11-11: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0)
Shutdown Event ECCPASE bit PWM Activity PWM Period Start of PWM Period ECCPASE Cleared by Shutdown Shutdown Firmware PWM Event Occurs Event Clears Resumes
11.4.5
AUTO-RESTART MODE
The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PRSEN bit in the PWM1CON register. If auto-restart is enabled, the ECCPASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the ECCPASE bit will be cleared via hardware and normal operation will resume.
FIGURE 11-12:
PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1)
Shutdown Event ECCPASE bit PWM Activity PWM Period Start of PWM Period Shutdown Shutdown Event Occurs Event Clears PWM Resumes
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11.4.6 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 11-13:
Period Pulse Width P1A(2) td P1B(2)
(1)
EXAMPLE OF HALFBRIDGE PWM OUTPUT
Period
In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shootthrough current) will flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. In Half-Bridge mode, a digitally programmable deadband delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 11-13 for illustration. The lower seven bits of the associated PWMxCON register (Register 11-3) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC).
td
(1)
(1)
td = Dead-Band Delay Note 1: 2: At this time, the TMR2 register is equal to the PR2 register. Output signals are shown as active-high.
FIGURE 11-14:
EXAMPLE OF HALF-BRIDGE APPLICATIONS
V+
Standard Half-Bridge Circuit ("Push-Pull") FET Driver P1A
+ V Load
FET Driver P1B
+ V -
V-
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REGISTER 11-3:
R/W-0 PRSEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PWM1CON: ENHANCED PWM CONTROL REGISTER
R/W-0 PDC6 R/W-0 PDC5 R/W-0 PDC4 R/W-0 PDC3 R/W-0 PDC2 R/W-0 PDC1 R/W-0 PDC0 bit 0
PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM PDC<6:0>: PWM Delay Count bits PDCn =Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active
bit 6-0
TABLE 11-7:
Name APFCON CCP1CON
(1)
SUMMARY OF REGISTERS ASSOCIATED WITH PWM
Bit 7 -- P1M Bit 6 -- -- Bit 5 -- DC1B1 Bit 4 T1GSEL DC1B0 Bit 3 -- Bit 2 -- Bit 1 P1BSEL Bit 0 P1ASEL Value on POR, BOR Value on all other Resets
---0 --00 ---0 --00
CCP1M3 CCP1M2 CCP1M1
CCP1M0 0-00 0000 0-00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
CCPR1L(1) CCPR1H(1) CMCON0 CMCON1 ECCPAS(1) PWM1CON INTCON PIE1 PIR1 T2CON(1) TMR2(1) TRISIO
Capture/Compare/PWM Register 1 Low Byte Capture/Compare/PWM Register 1 High Byte CMON -- PRSEN GIE -- -- -- -- COUT -- PDC6 PEIE ADIE(1) ADIF(1) CMOE -- PDC5 T0IE CCP1IE(1) CCP1IF(1) CMPOL T1ACS PDC4 INTE -- -- -- CMHYS PSSAC1 PDC3 GPIE CMIE CMIF CMR -- PSSAC0 PDC2 T0IF -- -- -- T1GSS PSSBD1 PDC1 INTF TMR2IE(1) TMR2IF(1) CMCH PSSBD0 PDC0 GPIF TMR1IE TMR1IF
0000 -0-0 0000 -0-0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -00- 0-00 -00- 0-00 -00- 0-00 -00- 0-00
CMSYNC ---0 0-10 ---0 0-10
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 0000 0000 0000 0000 TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 --
Timer2 Module Register
Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the PWM. Note 1: For PIC12F615/617/HV615 only.
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NOTES:
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12.0 SPECIAL FEATURES OF THE CPU
12.1 Configuration Bits
The Configuration bits can be programmed (read as `0'), or left unprogrammed (read as `1') to select various device configurations as shown in Register 12-1. These bits are mapped in program memory location 2007h. Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h3FFFh), which can be accessed only during programming. See Memory Programming Specification (DS41204) for more information.
The PIC12F609/615/617/12HV609/615 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving features and offer code protection. These features are: * Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Oscillator selection * Sleep * Code protection * ID Locations * In-Circuit Serial Programming The PIC12F609/615/617/12HV609/615 has two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 64 ms (nominal) on power-up only, designed to keep the part in Reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which can use the Powerup Timer to provide at least a 64 ms Reset. With these three functions-on-chip, most applications need no external Reset circuitry. The Sleep mode is designed to offer a very low-current Power-Down mode. The user can wake-up from Sleep through: * External Reset * Watchdog Timer Wake-up * An interrupt Several oscillator options are also made available to allow the part to fit the application. The INTOSC option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options (see Register 12-1).
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REGISTER 12-1: CONFIG: CONFIGURATION WORD REGISTER (ADDRESS: 2007h) FOR PIC12F609/615/HV609/615 ONLY
U-1 -- R/P-1 BOREN1
(1)
U-1 -- bit 13
U-1 --
U-1 --
R/P-1 BOREN0
(1)
R/P-1
R/P-1
(2)
R/P-1 MCLRE
(3)
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
IOSCFS CP
PWRTE WDTE FOSC2 FOSC1 FOSC0 bit 0
Legend: R = Readable bit -n = Value at POR bit 13-10 bit 9-8 W = Writable bit `1' = Bit is set P = Programmable `0' = Bit is cleared U = Unimplemented bit, read as `0' x = Bit is unknown
Unimplemented: Read as `1' BOREN<1:0>: Brown-out Reset Selection bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 0x = BOR disabled IOSCFS: Internal Oscillator Frequency Select bit 1 = 8 MHz 0 = 4 MHz CP: Code Protection bit(2) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled MCLRE: MCLR Pin Function Select bit(3) 1 = MCLR pin function is MCLR 0 = MCLR pin function is digital input, MCLR internally tied to VDD PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC<2:0>: Oscillator Selection bits 111 =RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN 110 =RCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN 101 =INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN 100 = INTOSCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN 011 =EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN 010 =HS oscillator: High-speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire program memory will be erased when the code protection is turned off. When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1: 2: 3:
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REGISTER 12-2:
U-1 -- bit 13 bit 13-12 bit 11-10 Unimplemented: Read as `1' WRT<1:0>: Flash Program Memory Self Write Enable bits 11 = Write protection off 10 = 000h to 1FFh write protected, 200h to 7FFh may be modified by PMCON1 control 01 = 000h to 3FFh write protected, 400h to 7FFh may be modified by PMCON1 control 00 = 000h to 7FFh write protected, entire program memory is write protected. BOREN<1:0>: Brown-out Reset Enable bits 11 = BOR enabled 10 = BOR disabled during Sleep and enabled during operation 0X = BOR disabled IOSCFS: Internal Oscillator Frequency Select 1 = 8 MHz 0 = 4 MHz CP: Code Protection 1 = Program memory is not code protected 0 = Program memory is external read and write protected MCLRE: MCLR Pin Function Select 1 = MCLR pin is MCLR function and weak internal pull-up is enabled 0 = MCLR pin is alternate function, MCLR function is internally disabled PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC<2:0>: Oscillator Selection bits 000 =LP oscillator: Low-power crystal on RA5/T1CKI/OSC1/CLKIN and RA4/AN3/T1G/OSC2/CLKOUT 001 =XT oscillator: Crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/AN3/T1G/OSC2/CLKOUT 010 =HS oscillator: High-speed crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/AN3/T1G/OSC2/CLKOUT 011 =EC: I/O function on RA4/AN3/T1G/OSC2/CLKOUT, CLKIN on RA5/T1CKI/OSC1/CLKIN 100 =INTOSCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT, I/O function on RA5/T1CKI/OSC1/CLKIN 101 =INTOSC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT, I/O function on RA5/T1CKI/OSC1/ CLKIN 110 =EXTRCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT, RC on RA5/T1CKI/OSC1/CLKIN 111 =EXTRC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT, RC on RA5/T1CKI/OSC1/CLKIN U-1 -- R/P-1
CONFIG - CONFIGURATION WORD (ADDRESS: 2007h) FOR PIC12F617 ONLY
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CP R/P-1 MCLRE R/P-1 PWRTE R/P-1 R/P-1 R/P-1 R/P-1 bit 0
WRT1 WRT0 BOREN1 BOREN0 IOSCFS
WDTE FOSC2 F0SC1 F0SC0
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:Enabling Brown-out Reset does not automatically enable the Power-up Timer (PWRT). Legend: R = Readable bit -n = Value at POR W = Writable bit 1 = bit is set U = Unimplemented bit, read as `1' 0 = bit is cleared P = Programmable x = bit is unknown
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12.2 Calibration Bits
The 8 MHz internal oscillator is factory calibrated. These calibration values are stored in fuses located in the Calibration Word (2008h). The Calibration Word is not erased when using the specified bulk erase sequence in the Memory Programming Specification (DS41204) and thus, does not require reprogramming. Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a "Reset state" on: * * * * * Power-on Reset MCLR Reset MCLR Reset during Sleep WDT Reset Brown-out Reset (BOR)
12.3
Reset
The PIC12F609/615/617/12HV609/615 device differentiates between various kinds of Reset: a) b) c) d) e) f) Power-on Reset (POR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Reset (BOR)
WDT wake-up does not cause register resets in the same manner as a WDT Reset since wake-up is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 12-2. Software can use these bits to determine the nature of the Reset. See Table 12-5 for a full description of Reset states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 12-1. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 16.0 "Electrical Specifications" for pulse-width specifications.
FIGURE 12-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR/VPP pin Sleep WDT Module VDD Rise Detect VDD Brown-out(1) Reset Power-on Reset WDT Time-out Reset
BOREN
S
OST/PWRT OST 10-bit Ripple Counter OSC1/ CLKIN pin PWRT On-Chip RC OSC 11-bit Ripple Counter R Q Chip_Reset
Enable PWRT Enable OST
Note
1:
Refer to the Configuration Word register (Register 12-1).
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PIC12F609/615/617/12HV609/615
12.3.1 POWER-ON RESET (POR) FIGURE 12-2:
VDD
The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Section 16.0 "Electrical Specifications" for details. If the BOR is enabled, the maximum rise time specification does not apply. The BOR circuitry will keep the device in Reset until VDD reaches VBOR (see Section 12.3.4 "Brown-out Reset (BOR)"). Note: The POR circuit does not produce an internal Reset when VDD declines. To reenable the POR, VDD must reach Vss for a minimum of 100 s.
RECOMMENDED MCLR CIRCUIT
R1 1 kor greater) R2
PIC(R) MCU
MCLR SW1 (optional) 100 needed with capacitor) C1 0.1 F (optional, not critical)
When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure proper operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting" (DS00607).
12.3.3
POWER-UP TIMER (PWRT)
12.3.2
MCLR
PIC12F609/615/617/12HV609/615 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. Voltages applied to the MCLR pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 12-2, is suggested. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When MCLRE = 0, the Reset signal to the chip is generated internally. When the MCLRE = 1, the GP3/MCLR pin becomes an external Reset input. In this mode, the GP3/MCLR pin has a weak pull-up to VDD.
The Power-up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR or Brown-out Reset. The Power-up Timer operates from an internal RC oscillator. For more information, see Section 4.4 "Internal Clock Modes". The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A Configuration bit, PWRTE, can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should be enabled when Brown-out Reset is enabled, although it is not required. The Power-up Timer delay will vary from chip-to-chip due to: * VDD variation * Temperature variation * Process variation See DC parameters for details "Electrical Specifications"). (Section 16.0
Note:
Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin, rather than pulling this pin directly to VSS.
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12.3.4 BROWN-OUT RESET (BOR)
The BOREN0 and BOREN1 bits in the Configuration Word register select one of three BOR modes. One mode has been added to allow control of the BOR enable for lower current during Sleep. By selecting BOREN<1:0> = 10, the BOR is automatically disabled in Sleep to conserve power and enabled on wake-up. See Register 12-1 for the Configuration Word definition. A brown-out occurs when VDD falls below VBOR for greater than parameter TBOR (see Section 16.0 "Electrical Specifications"). The brown-out condition will reset the device. This will occur regardless of VDD slew rate. A Brown-out Reset may not occur if VDD falls below VBOR for less than parameter TBOR. On any Reset (Power-on, Brown-out Reset, Watchdog timer, etc.), the chip will remain in Reset until VDD rises above VBOR (see Figure 12-3). If enabled, the Powerup Timer will be invoked by the Reset and keep the chip in Reset an additional 64 ms. Note: The Power-up Timer is enabled by the PWRTE bit in the Configuration Word register.
If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above VBOR, the Power-up Timer will execute a 64 ms Reset.
FIGURE 12-3:
VDD
BROWN-OUT SITUATIONS
VBOR
Internal Reset VDD
64 ms(1)
VBOR < 64 ms
Internal Reset
64 ms(1)
VDD
VBOR
Internal Reset Note 1: 64 ms delay only if PWRTE bit is programmed to `0'.
64 ms(1)
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12.3.5 TIME-OUT SEQUENCE 12.3.6
On power-up, the time-out sequence is as follows: * PWRT time-out is invoked after POR has expired. * OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 12-4, Figure 12-5 and Figure 12-6 depict time-out sequences. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then, bringing MCLR high will begin execution immediately (see Figure 12-5). This is useful for testing purposes or to synchronize more than one PIC12F609/615/617/ 12HV609/615 device operating in parallel. Table 12-6 shows the Reset conditions for some special registers, while Table 12-5 shows the Reset conditions for all the registers.
POWER CONTROL (PCON) REGISTER
The Power Control register PCON (address 8Eh) has two Status bits to indicate what type of Reset occurred last. Bit 0 is BOR (Brown-out). BOR is unknown on Poweron Reset. It must then be set by the user and checked on subsequent Resets to see if BOR = 0, indicating that a Brown-out has occurred. The BOR Status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (BOREN<1:0> = 00 in the Configuration Word register). Bit 1 is POR (Power-on Reset). It is a `0' on Power-on Reset and unaffected otherwise. The user must write a `1' to this bit following a Power-on Reset. On a subsequent Reset, if POR is `0', it will indicate that a Poweron Reset has occurred (i.e., VDD may have gone too low). For more information, see Section 12.3.4 "Brown-out Reset (BOR)".
TABLE 12-1:
TIME-OUT IN VARIOUS SITUATIONS
Power-up Brown-out Reset PWRTE = 0 TPWRT + 1024 * TOSC TPWRT PWRTE = 1 1024 * TOSC -- Wake-up from Sleep 1024 * TOSC --
Oscillator Configuration PWRTE = 0 XT, HS, LP RC, EC, INTOSC TPWRT + 1024 * TOSC TPWRT PWRTE = 1 1024 * TOSC --
TABLE 12-2:
POR 0 u u u u u x 0 u u u u
STATUS/PCON BITS AND THEIR SIGNIFICANCE
TO 1 1 0 0 u 1 PD 1 1 u 0 u 0 Power-on Reset Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during Sleep Condition
BOR
Legend: u = unchanged, x = unknown
TABLE 12-3:
Name PCON STATUS Bit 7 -- IRP
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET
Bit 6 -- RP1 Bit 5 -- RP0 Bit 4 -- TO Bit 3 -- PD Bit 2 -- Z Bit 1 POR DC Bit 0 BOR C Value on POR, BOR Value on all other Resets(1)
---- --qq ---- --uu 0001 1xxx 000q quuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. Shaded cells are not used by BOR. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
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FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 12-5:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2
VDD MCLR Internal POR TPWRT PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 12-6:
VDD MCLR Internal POR
TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)
TPWRT PWRT Time-out
TOST
OST Time-out
Internal Reset
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TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS (PIC12F609/HV609)
Power-on Reset xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --x0 x000 ---0 0000 0000 0000 ----- 0--0 xxxx xxxx xxxx xxxx 0000 0000 0-00 0000 0000 -0-0 ---0 0-10 1111 1111 --11 1111 ----- 0--0 ---- --0x ---0 0000 --11 -111 --00 0000 ---- 1-11 MCLR Reset WDT Reset Brown-out Reset(1) uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 000q quuu(4) uuuu uuuu --u0 u000 ---0 0000 0000 0000 ---- 0--0 uuuu uuuu uuuu uuuu uuuu uuuu 0-00 0000 0000 -0-0 ---0 0-10 1111 1111 --11 1111 ---- 0--0 ---- --uu(1, 5) ---u uuuu --11 -111 --00 0000 ---- 1-11 Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out uuuu uuuu uuuu uuuu uuuu uuuu PC + 1(3) uuuq quuu(4) uuuu uuuu --uu uuuu ---u uuuu uuuu uuuu(2) ---- u--u(2) uuuu uuuu uuuu uuuu -uuu uuuu u-uu uuuu uuuu -u-u ---u u-qu uuuu uuuu --uu uuuu ---- u--u ---- --uu ---u uuuu --uu -uuu --uu uuuu ---- q-qq
Register
Address
W INDF TMR0 PCL STATUS FSR GPIO PCLATH INTCON PIR1 TMR1L TMR1H T1CON VRCON CMCON0 CMCON1 OPTION_REG TRISIO PIE1 PCON OSCTUNE WPU IOC ANSEL Legend: Note 1: 2: 3: 4: 5:
-- 00h/80h 01h 02h/82h 03h/83h 04h/84h 05h 0Ah/8Ah 0Bh/8Bh 0Ch 0Eh 0Fh 10h 19h 1Ah 1Ch 81h 85h 8Ch 8Eh 90h 95h 96h 9Fh
u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 12-6 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
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TABLE 12-5: INITIALIZATION CONDITION FOR REGISTERS (PIC12F615/617/HV615)
MCLR Reset WDT Reset Brown-out Reset(1) uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 000q quuu(4) uuuu uuuu --u0 u000 ---0 0000 0000 0000 -000 0-00 uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 -000 0000 uuuu uuuu uuuu uuuu 0-00 0000 0000 0000 0000 0000 0-00 0000 0000 -0-0 ---0 0-10 uuuu uuuu 00-0 0000 1111 1111 --11 1111 -00- 0-00 ---- --uu(1, 5) ---u uuuu 1111 1111 ---0 --00 --11 -111 --00 0000 ---- -000 ---- ---0000 0000 Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out uuuu uuuu uuuu uuuu uuuu uuuu PC + 1(3) uuuq quuu(4) uuuu uuuu --uu uuuu ---u uuuu uuuu uuuu(2) -uuu u-uu(2) uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu -u-u ---u u-qu uuuu uuuu uu-u uuuu uuuu uuuu --uu uuuu -uu- u-uu ---- --uu ---u uuuu 1111 1111 ---u --uu --uu -uuu --uu uuuu ---- -uuu ---- ---uuuu uuuu
Register
Address
Power-on Reset
W INDF TMR0 PCL STATUS FSR GPIO PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2
(1)
-- 00h/80h 01h 02h/82h 03h/83h 04h/84h 05h 0Ah/8Ah 0Bh/8Bh 0Ch 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 19h 1Ah 1Ch 1Eh 1Fh 81h 85h 8Ch 8Eh 90h 92h 93h 95h 96h
(6) (1)
xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --x0 x000 ---0 0000 0000 0000 -000 0-00 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 -000 0000 xxxx xxxx xxxx xxxx 0-00 0000 0000 0000 0000 0000 0-00 0000 0000 -0-0 ---0 0-10 xxxx xxxx 00-0 0000 1111 1111 --11 1111 -00- 0-00 ---- --0x ---0 0000 1111 1111 ---0 --00 --11 -111 --00 0000 ---- -000 ---- ---0000 0000
T2CON(1) CCPR1L CCPR1H(1) CCP1CON(1) PWM1CON(1) ECCPAS(1) VRCON CMCON0 CMCON1 ADRESH
(1)
ADCON0(1) OPTION_REG TRISIO PIE1 PCON OSCTUNE PR2 APFCON WPU IOC PMCON1 PMCON2(6) PMADRL(6) Legend: Note 1: 2: 3: 4: 5: 6:
98h 99h 9Ah
u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 12-6 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. For PIC12F617 only.
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TABLE 12-5: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)(PIC12F615/617/HV615)
MCLR Reset WDT Reset (Continued) Brown-out Reset(1) ---- -000 0000 0000 --00 0000 uuuu uuuu -000 1111 Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out (Continued) ---- -uuu uuuu uuuu --uu uuuu uuuu uuuu -uuu qqqq
Register
Address
Power-on Reset
PMADRH(6) PMDATL
(6)
9Bh 9Ch 9Dh 9Eh 9Fh
---- -000 0000 0000 --00 0000 xxxx xxxx -000 1111
PMDATH(6) ADRESL(1) ANSEL Legend: Note 1: 2: 3: 4: 5: 6:
u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 12-6 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. For PIC12F617 only.
TABLE 12-6:
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Condition Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1
(1)
Status Register 0001 1xxx 000u uuuu 0001 0uuu 0000 uuuu uuu0 0uuu 0001 1uuu uuu1 0uuu
PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --10 ---- --uu
Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from Sleep
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
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12.4 Interrupts
The PIC12F609/615/617/12HV609/615 has 8 sources of interrupt: External Interrupt GP2/INT Timer0 Overflow Interrupt GPIO Change Interrupts Comparator Interrupt A/D Interrupt (PIC12F615/617/HV615 only) Timer1 Overflow Interrupt Timer2 Match Interrupt (PIC12F615/617/HV615 only) * Enhanced CCP Interrupt (PIC12F615/617/HV615 only) * Flash Memory Self Write (PIC12F617 only) The Interrupt Control register (INTCON) and Peripheral Interrupt Request Register 1 (PIR1) record individual interrupt requests in flag bits. The INTCON register also has individual and global interrupt enable bits. The Global Interrupt Enable bit, GIE of the INTCON register, enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in the INTCON register and PIE1 register. GIE is cleared on Reset. When an interrupt is serviced, the following actions occur automatically: * The GIE is cleared to disable any further interrupt. * The return address is pushed onto the stack. * The PC is loaded with 0004h. The Return from Interrupt instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables unmasked interrupts. The following interrupt flags are contained in the INTCON register: * INT Pin Interrupt * GPIO Change Interrupt * Timer0 Overflow Interrupt The peripheral interrupt flags are contained in the special register, PIR1. The corresponding interrupt enable bit is contained in special register, PIE1. The following interrupt flags are contained in the PIR1 register: * * * * * A/D Interrupt Comparator Interrupt Timer1 Overflow Interrupt Timer2 Match Interrupt Enhanced CCP Interrupt * * * * * * * Figure 12-8). The latency is the same for one or twocycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Note 1: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The interrupts, which were ignored, are still pending to be serviced when the GIE bit is set again. For additional information on Timer1, Timer2, comparators, ADC, Enhanced CCP modules, refer to the respective peripheral section.
12.4.1
GP2/INT INTERRUPT
The external interrupt on the GP2/INT pin is edgetriggered; either on the rising edge if the INTEDG bit of the OPTION register is set, or the falling edge, if the INTEDG bit is clear. When a valid edge appears on the GP2/INT pin, the INTF bit of the INTCON register is set. This interrupt can be disabled by clearing the INTE control bit of the INTCON register. The INTF bit must be cleared by software in the Interrupt Service Routine before re-enabling this interrupt. The GP2/INT interrupt can wake-up the processor from Sleep, if the INTE bit was set prior to going into Sleep. See Section 12.7 "Power-Down Mode (Sleep)" for details on Sleep and Figure 12-9 for timing of wake-up from Sleep through GP2/INT interrupt. Note: The ANSEL register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0' and cannot generate an interrupt.
For external interrupt events, such as the INT pin or GPIO change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (see
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12.4.2 TIMER0 INTERRUPT 12.4.3 GPIO INTERRUPT-ON-CHANGE
An overflow (FFh 00h) in the TMR0 register will set the T0IF bit of the INTCON register. The interrupt can be enabled/disabled by setting/clearing T0IE bit of the INTCON register. See Section 6.0 "Timer0 Module" for operation of the Timer0 module. An input change on GPIO sets the GPIF bit of the INTCON register. The interrupt can be enabled/ disabled by setting/clearing the GPIE bit of the INTCON register. Plus, individual pins can be configured through the IOC register. Note: If a change on the I/O pin should occur when any GPIO operation is being executed, then the GPIF interrupt flag may not get set.
FIGURE 12-7:
INTERRUPT LOGIC
IOC-GP0 IOC0 IOC-GP1 IOC1 IOC-GP2 IOC2 IOC-GP3 IOC3 IOC-GP4 IOC4 IOC-GP5 IOC5
(615/617 only) TMR2IF
TMR2IE TMR1IF TMR1IE CMIF CMIE
T0IF T0IE INTF INTE GPIF GPIE PEIE GIE
Wake-up (If in Sleep mode)(1)
Interrupt to CPU
(615/617 only) ADIF (615/617 only) CCP1IF
ADIE
CCP1IE
Note 1:
Some peripherals depend upon the system clock for operation. Since the system clock is suspended during Sleep, only those peripherals which do not depend upon the system clock will wake the part from Sleep. See Section 12.7.1 "Wake-up from Sleep".
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FIGURE 12-8: INT PIN INTERRUPT TIMING
Q1 Q2 OSC1 CLKOUT (3)
(4)
Q3
Q4 Q1 Q2
Q3 Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3 Q4
Q1
Q2
Q3
Q4
INT pin INTF flag (INTCON reg.) GIE bit (INTCON reg.) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed
Note 1: 2: 3: 4: 5:
(1) (5)
(1)
Interrupt Latency (2)
PC
PC + 1 Inst (PC + 1) Inst (PC)
PC + 1 -- Dummy Cycle
0004h Inst (0004h) Dummy Cycle
0005h Inst (0005h) Inst (0004h)
Inst (PC) Inst (PC - 1)
INTF flag is sampled here (every Q1). Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. CLKOUT is available only in INTOSC and RC Oscillator modes. For minimum width of INT pulse, refer to AC specifications in Section 16.0 "Electrical Specifications". INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 12-7:
Name INTCON IOC PIR1 PIE1 Bit 7 GIE -- -- --
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Bit 6 PEIE -- ADIE(1) Bit 5 T0IE IOC5 CCP1IE(1) Bit 4 INTE IOC4
-- --
Bit 3 GPIE IOC3 CMIF CMIE
Bit 2 T0IF IOC2 -- --
Bit 1 INTF IOC1 TMR2IF(1)
Bit 0 GPIF IOC0 TMR1IF
Value on POR, BOR
Value on all other Resets
0000 0000 0000 0000 --00 0000 --00 0000 -00- 0-00 -000 0-00
ADIF(1) CCP1IF(1)
TMR2IE(1) TMR1IE -00- 0-00 -000 0-00
Legend: x = unknown, u = unchanged, - = unimplemented read as `0', q = value depends upon condition. Shaded cells are not used by the interrupt module. Note 1: PIC12F615/617/HV615 only.
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12.5 Context Saving During Interrupts
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Temporary holding registers W_TEMP and STATUS_TEMP should be placed in the last 16 bytes of GPR (see Figure 2-3). These 16 locations are common to all banks and do not require banking. This makes context save and restore operations simpler. The code shown in Example 12-1 can be used to: * * * * * Store the W register Store the STATUS register Execute the ISR code Restore the Status (and Bank Select Bit register) Restore the W register Note: The PIC12F609/615/617/12HV609/615 does not require saving the PCLATH. However, if computed GOTOs are used in both the ISR and the main code, the PCLATH must be saved and restored in the ISR.
EXAMPLE 12-1:
MOVWF SWAPF
SAVING STATUS AND W REGISTERS IN RAM
;Copy W to TEMP ;Swap status to ;Swaps are used ;Save status to register be saved into W because they do not affect the status bits bank zero STATUS_TEMP register
W_TEMP STATUS,W
MOVWF STATUS_TEMP : :(ISR) : SWAPF STATUS_TEMP,W MOVWF SWAPF SWAPF STATUS W_TEMP,F W_TEMP,W
;Insert user code here ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W
12.6
Watchdog Timer (WDT)
12.6.1
WDT PERIOD
The Watchdog Timer is a free running, on-chip RC oscillator, which requires no external components. This RC oscillator is separate from the external RC oscillator of the CLKIN pin and INTOSC. That means that the WDT will run, even if the clock on the OSC1 and OSC2 pins of the device has been stopped (for example, by execution of a SLEEP instruction). During normal operation, a WDT time out generates a device Reset. If the device is in Sleep mode, a WDT time out causes the device to wake-up and continue with normal operation. The WDT can be permanently disabled by programming the Configuration bit, WDTE, as clear (Section 12.1 "Configuration Bits").
The WDT has a nominal time-out period of 18 ms (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the prescaler, if assigned to the WDT, and prevent it from timing out and generating a device Reset. The TO bit in the STATUS register will be cleared upon a Watchdog Timer time out.
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12.6.2 WDT PROGRAMMING CONSIDERATIONS
It should also be taken in account that under worstcase conditions (i.e., VDD = Min., Temperature = Max., Max. WDT prescaler) it may take several seconds before a WDT time out occurs.
FIGURE 12-2:
CLKOUT (= FOSC/4)
WATCHDOG TIMER BLOCK DIAGRAM
Data Bus 0 1 1 SYNC 2 Cycles 0 0 TMR0 8
T0CKI pin T0SE T0CS
8-bit Prescaler 1 8 3 PS<2:0>
Set Flag bit T0IF on Overflow PSA
PSA
1 WDT Time-Out 0
Watchdog Timer
WDTE Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
PSA
TABLE 12-8:
WDTE = 0 CLRWDT Command
WDT STATUS
Conditions WDT
Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK Exit Sleep + System Clock = XT, HS, LP
Cleared
Cleared until the end of OST
TABLE 12-9:
Name OPTION_REG CONFIG Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Bit 7 GPPU IOSCFS Bit 6 INTEDG CP Bit 5 T0CS MCLRE Bit 4 T0SE PWRTE Bit 3 PSA WDTE Bit 2 PS2 FOSC2 Bit 1 PS1 FOSC1 Bit 0 PS0 FOSC0 Value on POR, BOR 1111 1111 -- Value on all other Resets 1111 1111 --
Shaded cells are not used by the Watchdog Timer. See Register 12-1 for operation of all Configuration Word register bits.
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12.7 Power-Down Mode (Sleep)
The Power-Down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: * * * * * WDT will be cleared but keeps running. PD bit in the STATUS register is cleared. TO bit is set. Oscillator driver is turned off. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance). When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is cleared) and any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wake-up from Sleep.
For lowest current consumption in this mode, all I/O pins should be either at VDD or VSS, with no external circuitry drawing current from the I/O pin and the comparators and CVREF should be disabled. I/O pins that are highimpedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pullups on GPIO should be considered. The MCLR pin must be at a logic high level. Note: It should be noted that a Reset generated by a WDT time-out does not drive MCLR pin low.
The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up.
12.7.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will Immediately wake-up from Sleep. The SLEEP instruction is executed. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. See Figure 12-9 for more details.
12.7.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the following events: 1. 2. 3. External Reset input on MCLR pin. Watchdog Timer wake-up (if WDT was enabled). Interrupt from GP2/INT pin, GPIO change or a peripheral interrupt.
The first event will cause a device Reset. The two latter events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT wake-up occurred. The following peripheral interrupts can wake the device from Sleep: 1. 2. 3. 4. 5. 6. Timer1 interrupt. Timer1 must be operating as an asynchronous counter. ECCP Capture mode interrupt. A/D conversion (when A/D clock source is RC). Comparator output changes state. Interrupt-on-change. External Interrupt from INT pin.
Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present.
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FIGURE 12-9: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 CLKOUT(4) INT pin INTF flag (INTCON reg.) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: Processor in Sleep Interrupt Latency (3)
PC Inst(PC) = Sleep Inst(PC - 1)
PC + 1 Inst(PC + 1) Sleep
PC + 2
PC + 2 Inst(PC + 2) Inst(PC + 1)
PC + 2
0004h Inst(0004h)
0005h Inst(0005h) Inst(0004h)
Dummy Cycle
Dummy Cycle
XT, HS or LP Oscillator mode assumed. TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC, INTOSC and RC Oscillator modes. GIE = `1' assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = `0', execution will continue in-line. CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
12.8
Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSPTM for verification purposes. Note: The entire Flash program memory will be erased when the code protection is turned off. See the MemoryProgramming Specification (DS41204) for more information.
12.9
ID Locations
Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used.
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12.10 In-Circuit Serial ProgrammingTM
ThePIC12F609/615/617/12HV609/615 microcontrollers can be serially programmed while in the end application circuit. This is simply done with five connections for: * * * * * clock data power ground programming voltage
12.11 In-Circuit Debugger
Since in-circuit debugging requires access to three pins, MPLAB(R) ICD 2 development with an 14-pin device is not practical. A special 28-pin PIC12F609/615/617/ 12HV609/615 ICD device is used with MPLAB ICD 2 to provide separate clock, data and MCLR pins and frees all normally available pins to the user. A special debugging adapter allows the ICD device to be used in place of a PIC12F609/615/617/12HV609/ 615 device. The debugging adapter is the only source of the ICD device. When the ICD pin on the PIC12F609/615/617/ 12HV609/615 ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2. When the microcontroller has this feature enabled, some of the resources are not available for general use. Table 12-10 shows which features are consumed by the background debugger.
This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a Program/Verify mode by holding the GP0 and GP1 pins low, while raising the MCLR (VPP) pin from VIL to VIHH. See the Memory Programming Specification (DS41284) for more information. GP0 becomes the programming data and GP1 becomes the programming clock. Both GP0 and GP1 are Schmitt Trigger inputs in Program/Verify mode. A typical In-Circuit Serial Programming connection is shown in Figure 12-10.
TABLE 12-10: DEBUGGER RESOURCES
Resource I/O pins Stack Program Memory Description ICDCLK, ICDDATA 1 level Address 0h must be NOP 700h-7FFh
FIGURE 12-10:
TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections
For more information, see "MPLAB(R) ICD 2 In-Circuit Debugger User's Guide" (DS51331), available on Microchip's web site (www.microchip.com).
External Connector Signals +5V 0V VPP CLK Data I/O
FIGURE 12-11:
PIC12F617/ PIC12F615/12HV615 PIC12F609/12HV609 VDD VSS MCLR/VPP/GP3/RA3 GP1 GP0
28 PIN ICD PINOUT
*
28-Pin PDIP In-Circuit Debug Device
VDD CS0 CS1 CS2 RA5 RA4 RA3 RC5 RC4 RC3 NC ICDCLK ICDMCLR ICDDATA
1 2 3 28 27 26
6 7 8 9 10 11 12 13 14
PIC16F616-ICD
4 5
25 24 23 22 21 20 19 18 17 16 15
*
*
*
To Normal Connections
* Isolation devices (as required)
GND RA0 RA1 SHUNTEN RA2 RC0 RC1 RC2 NC NC NC NC NC ICD
Note:
To erase the device VDD must be above the Bulk Erase VDD minimum given in the Memory Programming Specification (DS41284)
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NOTES:
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13.0 VOLTAGE REGULATOR
The PIC12HV609/HV615 devices include a permanent internal 5 volt (nominal) shunt regulator in parallel with the VDD pin. This eliminates the need for an external voltage regulator in systems sourced by an unregulated supply. All external devices connected directly to the VDD pin will share the regulated supply voltage and contribute to the total VDD supply current (ILOAD). An external current limiting resistor, RSER, located between the unregulated supply, VUNREG, and the VDD pin, drops the difference in voltage between VUNREG and VDD. RSER must be between RMAX and RMIN as defined by Equation 13-1.
EQUATION 13-1:
RMAX =
RSER LIMITING RESISTOR
(VUMIN - 5V) 1.05 * (4 MA + ILOAD)
13.1
Regulator Operation
RMIN = (VUMAX - 5V) 0.95 * (50 MA)
A shunt regulator generates a specific supply voltage by creating a voltage drop across a pass resistor RSER. The voltage at the VDD pin of the microcontroller is monitored and compared to an internal voltage reference. The current through the resistor is then adjusted, based on the result of the comparison, to produce a voltage drop equal to the difference between the supply voltage VUNREG and the VDD of the microcontroller. See Figure 13-1 for voltage regulator schematic.
Where: RMAX = maximum value of RSER (ohms) RMIN = minimum value of RSER (ohms) VUMIN = minimum value of VUNREG VUMAX = maximum value of VUNREG VDD = regulated voltage (5V nominal) ILOAD = maximum expected load current in mA including I/O pin currents and external circuits connected to VDD. 1.05 = compensation for +5% tolerance of RSER = compensation for -5% tolerance of RSER 0.95
FIGURE 13-1:
VUNREG RSER
VOLTAGE REGULATOR
ILOAD VDD
ISUPPLY
CBYPASS
ISHUNT
Feedback VSS Device
13.2
Regulator Considerations
The supply voltage VUNREG and load current are not constant. Therefore, the current range of the regulator is limited. Selecting a value for RSER must take these three factors into consideration. Since the regulator uses the band gap voltage as the regulated voltage reference, this voltage reference is permanently enabled in the PIC12HV609/HV615 devices. The shunt regulator will still consume current when below operating voltage range for the shunt regulator.
13.3
Design Considerations
For more information on using the shunt regulator and managing current load, see Application Note AN1035, "Designing with HV Microcontrollers" (DS01035).
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NOTES:
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14.0 INSTRUCTION SET SUMMARY
TABLE 14-1:
Field
f W b k x
The PIC12F609/615/617/12HV609/615 instruction set is highly orthogonal and is comprised of three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 14-1, while the various opcode fields are summarized in Table 14-1. Table 14-2 lists the instructions recognized by the MPASMTM assembler. For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the W register. If `d' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, `b' represents a bit field designator, which selects the bit affected by the operation, while `f' represents the address of the file in which the bit is located. For literal and control operations, `k' represents an 8-bit or 11-bit constant, or literal value. One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit.
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. Program Counter Time-out bit Carry bit Digit carry bit Zero bit Power-down bit
d
PC TO C DC Z PD
FIGURE 14-1:
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 8 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 7 k (literal)
0
0
14.1
Read-Modify-Write Operations
Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (RMW) operation. The register is read, the data is modified, and the result is stored according to either the instruction or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register. For example, a CLRF GPIO instruction will read GPIO, clear all the data bits, then write the result back to GPIO. This example would have the unintended consequence of clearing the condition that set the GPIF flag.
0
k = 11-bit immediate value
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TABLE 14-2:
Mnemonic, Operands
PIC12F609/615/617/12HV609/615 INSTRUCTION SET
14-Bit Opcode Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS LSb Status Affected Notes
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF
f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d
Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f
1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C, DC, Z Z Z Z Z Z Z Z Z
1, 2 1, 2 2 1, 2 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2 1, 2
C C C, DC, Z Z
1, 2 1, 2 1, 2 1, 2 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: f, b f, b f, b f, b k k k - k k k - k - - k k Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call Subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff C, DC, Z Z TO, PD Z 1, 2 1, 2 3 3
LITERAL AND CONTROL OPERATIONS 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk
TO, PD C, DC, Z Z
2: 3:
When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
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14.2
ADDLW Syntax: Operands: Operation: Status Affected: Description:
Instruction Descriptions
Add literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight-bit literal `k' and the result is placed in the W register. Operation: Status Affected: Description: k BCF Syntax: Operands: Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None Bit `b' in register `f' is cleared. f,b
ADDWF Syntax: Operands: Operation: Status Affected: Description:
Add W and f [ label ] ADDWF 0 f 127 d 0,1 (W) + (f) (destination) C, DC, Z Add the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None Bit `b' in register `f' is set. f,b
ANDLW Syntax: Operands: Operation: Status Affected: Description:
AND literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. k
BTFSC Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None If bit `b' in register `f' is `1', the next instruction is executed. If bit `b' in register `f' is `0', the next instruction is discarded, and a NOP is executed instead, making this a two-cycle instruction.
ANDWF Syntax: Operands: Operation: Status Affected: Description:
AND W with f [ label ] ANDWF 0 f 127 d 0,1 (W) .AND. (f) (destination) Z AND the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
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BTFSS Syntax: Operands: Operation: Status Affected: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None If bit `b' in register `f' is `0', the next instruction is executed. If bit `b' is `1', then the next instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. Status Affected: Description: CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
CALL Syntax: Operands: Operation:
Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction.
COMF Syntax: Operands: Operation: Status Affected: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. f,d
Status Affected: Description:
CLRF Syntax: Operands: Operation: Status Affected: Description:
Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z The contents of register `f' are cleared and the Z bit is set. f
DECF Syntax: Operands: Operation: Status Affected: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'.
CLRW Syntax: Operands: Operation: Status Affected: Description:
Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
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DECFSZ Syntax: Operands: Operation: Status Affected: Description: Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a two-cycle instruction. INCFSZ Syntax: Operands: Operation: Status Affected: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a two-cycle instruction.
GOTO Syntax: Operands: Operation: Status Affected: Description:
Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction.
IORLW Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register.
INCF Syntax: Operands: Operation: Status Affected: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
IORWF Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
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MOVF Syntax: Operands: Operation: Status Affected: Description: Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z The contents of register `f' is moved to a destination dependent upon the status of `d'. If d = 0, destination is W register. If d = 1, the destination is file register `f' itself. d = 1 is useful to test a file register since Status flag Z is affected. 1 1
MOVF FSR, 0
MOVWF Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example:
Move W to f [ label ] (W) (f) None Move data from W register to register `f'. 1 1 MOVW F OPTION MOVWF f 0 f 127
Words: Cycles: Example:
Before Instruction OPTION = W = After Instruction OPTION = W =
0xFF 0x4F 0x4F 0x4F
After Instruction W= value in FSR register Z=1
MOVLW Syntax: Operands: Operation: Status Affected: Description:
Move literal to W [ label ] k (W) None The eight-bit literal `k' is loaded into W register. The "don't cares" will assemble as `0's. 1 1
MOVLW 0x5A
NOP Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example:
No Operation [ label ] None No operation None No operation. 1 1
NOP
MOVLW k
NOP
0 k 255
Words: Cycles: Example:
After Instruction W=
0x5A
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RETFIE Syntax: Operands: Operation: Status Affected: Description: Return from Interrupt [ label ] None TOS PC, 1 GIE None Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. 1 2
RETFIE
RETLW Syntax: Operands: Operation: Status Affected: Description:
Return with literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 1 2 CALL TABLE;W contains ;table offset ;value GOTO DONE * * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ;End of table Before Instruction W = 0x07 After Instruction W = value of k8
RETFIE
Words: Cycles: Example:
Words: Cycles: Example:
After Interrupt PC = GIE =
TOS 1
TABLE
DONE
RETURN Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
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RLF Syntax: Operands: Operation: Status Affected: Description: Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'.
C Register f
SLEEP Syntax: Operands: Operation:
Enter Sleep mode [ label ] SLEEP None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped.
RLF
f,d
Status Affected: Description:
Words: Cycles: Example:
1 1
RLF REG1,0 REG1 C = = = = = 1110 0110 0 1110 0110 1100 1100 1
Before Instruction
After Instruction
REG1 W C
RRF Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
C Register f
SUBLW Syntax: Operands: Operation: Description:
Subtract W from literal [ label ] SUBLW k 0 k 255 k - (W) W) The W register is subtracted (2's complement method) from the eight-bit literal `k'. The result is placed in the W register. Result C=0 C=1 DC = 0 DC = 1 Condition Wk Wk W<3:0> k<3:0> W<3:0> k<3:0>
Status Affected: C, DC, Z
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SUBWF Syntax: Operands: Operation: Description: Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) destination) Subtract (2's complement method) W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. C=0 C=1 DC = 0 DC = 1 Wf Wf W<3:0> f<3:0> W<3:0> f<3:0> XORWF Syntax: Operands: Operation: Status Affected: Description: Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) destination) Z Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
Status Affected: C, DC, Z
SWAPF Syntax: Operands: Operation: Status Affected: Description:
Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in register `f'.
XORLW Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k W) Z The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register.
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NOTES:
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15.0 DEVELOPMENT SUPPORT
15.1
The PIC(R) microcontrollers and dsPIC(R) digital signal controllers are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers - MPLAB ICD 3 - PICkitTM 3 Debug Express * Device Programmers - PICkitTM 2 Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either C or assembly) * One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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15.2 MPLAB C Compilers for Various Device Families 15.5 MPLINK Object Linker/ MPLIB Object Librarian
The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip's PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
15.3
HI-TECH C for Various Device Families
The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip's PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms.
15.6
MPLAB Assembler, Linker and Librarian for Various Device Families
15.4
MPASM Assembler
The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
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15.7 MPLAB SIM Software Simulator 15.9
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
MPLAB ICD 3 In-Circuit Debugger System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC(R) Flash microcontrollers and dsPIC(R) DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers.
15.8
MPLAB REAL ICE In-Circuit Emulator System
15.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and programming of PIC(R) and dsPIC(R) Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software.
MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
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15.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express
The PICkitTM 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip's Flash families of microcontrollers. The full featured Windows(R) programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip's powerful MPLAB Integrated Development Environment (IDE) the PICkitTM 2 enables in-circuit debugging on most PIC(R) microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software.
15.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
15.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications.
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16.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings()
Ambient temperature under bias..........................................................................................................-40 to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ............................................................................................................................... 800 mW Maximum current out of VSS pin ...................................................................................................................... 95 mA Maximum current into VDD pin ......................................................................................................................... 95 mA Input clamp current, IIK (VI < 0 or VI > VDD)20 mA Output clamp current, IOK (Vo < 0 or Vo >VDD)20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Maximum current sunk by GPIO ...................................................................................................................... 90 mA Maximum current sourced GPIO...................................................................................................................... 90 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL).
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.
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FIGURE 16-1: PIC12F609/615/617 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
5.5 5.0 4.5 VDD (V) 4.0 3.5 3.0 2.5 2.0 0 8 10 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 20
FIGURE 16-2:
PIC12HV609/615 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
5.0 4.5 VDD (V) 4.0 3.5 3.0 2.5 2.0 0 8 10 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 20
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16.1 DC Characteristics: PIC12F609/615/617/12HV609/615-I (Industrial) PIC12F609/615/617/12HV609/615-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
DC CHARACTERISTICS Param No. D001 D001 D001B D001B D001C D001C D001D D001D D002* D003 VDR VPOR
Sym VDD
Characteristic Supply Voltage PIC12F609/615/617 PIC12HV609/615 PIC12F609/615/617 PIC12HV609/615 PIC12F609/615/617 PIC12HV609/615 PIC12F609/615/617 PIC12HV609/615 RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal
2.0 2.0 2.0 2.0 3.0 3.0 4.5 4.5 1.5 --
-- -- -- -- -- -- -- -- -- VSS
5.5 --
(2)
V V V V V V V V V V
FOSC < = 4 MHz FOSC < = 4 MHz FOSC < = 8 MHz FOSC < = 8 MHz FOSC < = 10 MHz FOSC < = 10 MHz FOSC < = 20 MHz FOSC < = 20 MHz Device in Sleep mode See Section 12.3.1 "Power-on Reset (POR)" for details.
5.5 --(2) 5.5 --(2) 5.5 --(2) -- --
D004*
SVDD
0.05
--
--
V/ms See Section 12.3.1 "Power-on Reset (POR)" for details.
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: User defined. Voltage across the shunt regulator should not exceed 5V.
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16.2 DC Characteristics: PIC12F609/615/617-I (Industrial) PIC12F609/615/617-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Conditions Device Characteristics Supply Current (IDD)(1, 2) Min -- -- -- D011* -- -- -- D012 -- -- -- D013* -- -- -- D014 -- -- -- D016* -- -- -- D017 -- -- -- D018 -- -- -- D019 -- --
* Note 1: 2:
DC CHARACTERISTICS
Param No. D010
Typ 13 19 32 135 185 300 240 360 0.66 75 155 345 185 325 0.665 245 360 0.620 395 0.620 1.2 175 285 530 2.2 2.8
Max 25 29 51 225 285 405 360 505 1.0 110 255 530 255 475 1.0 340 485 0.845 550 0.850 1.6 235 390 750 3.1 3.35
Units VDD A A A A A A A A mA A A A A A mA A A mA A mA mA A A A mA mA 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 4.5 5.0 FOSC = 20 MHz HS Oscillator mode FOSC = 4 MHz EXTRC mode(3) FOSC = 8 MHz INTOSC mode FOSC = 4 MHz INTOSC mode FOSC = 4 MHz EC Oscillator mode FOSC = 1 MHz EC Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode Note FOSC = 32 kHz LP Oscillator mode
PIC12F609/615/617
3:
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-torail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in KOhms (K
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16.3 DC Characteristics: PIC12HV609/615-I (Industrial) PIC12HV609/615-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Conditions Device Characteristics Supply Current (IDD)(1, 2) Min -- -- -- D011* -- -- -- D012 -- -- -- D013* -- -- -- D014 -- -- -- D016* -- -- -- D017 -- -- -- D018 -- -- -- D019 -- Typ 160 240 280 270 400 520 380 575 0.875 215 375 570 330 550 0.85 310 500 0.74 460 0.75 1.2 320 510 0.770 2.5 Max 230 310 400 380 560 780 540 810 1.3 310 565 870 475 800 1.2 435 700 1.1 650 1.1 1.6 465 750 1.0 3.4 Units VDD A A A A A A A A mA A A A A A mA A A mA A mA mA A A mA mA 2.0 3.0 4.5 2.0 3.0 4.5 2.0 3.0 4.5 2.0 3.0 4.5 2.0 3.0 4.5 2.0 3.0 4.5 2.0 3.0 4.5 2.0 3.0 4.5 4.5 FOSC = 20 MHz HS Oscillator mode FOSC = 4 MHz EXTRC mode(3) FOSC = 8 MHz INTOSC mode FOSC = 4 MHz INTOSC mode FOSC = 4 MHz EC Oscillator mode FOSC = 1 MHz EC Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode Note FOSC = 32 kHz LP Oscillator mode
DC CHARACTERISTICS
Param No. D010
PIC12HV609/615
* These parameters are characterized but not tested. Data in "Typ" column is at 4.5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k
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16.4 DC Characteristics: PIC12F609/615/617 - I (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Conditions Device Characteristics Power-down Base Current (IPD)(2) PIC12F609/615/617 Min -- -- -- Typ 0.05 0.15 0.35 150 D021 -- -- -- D022 D023 -- -- -- -- -- D024 -- -- -- D025* -- -- -- D026 -- -- -- D027 -- -- 0.5 2.5 9.5 5.0 6.0 50 55 60 30 45 75 39 59 98 5.5 7.0 8.5 0.2 0.36 Max 0.9 1.2 1.5 500 1.5 4.0 17 9 12 60 65 75 40 60 105 50 80 130 10 12 14 1.6 1.9 Units VDD A A A nA A A A A A A A A A A A A A A A A A A A 2.0 3.0 5.0 3.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 A/D Current(1), no conversion in progress T1OSC Current(1), 32.768 kHz CVREF Current(1) (low range) CVREF Current(1) (high range) Comparator Current(1), single comparator enabled BOR Current(1)
-40C TA +25C for industrial
DC CHARACTERISTICS Param No. D020
Note WDT, BOR, Comparator, VREF and T1OSC disabled
WDT Current(1)
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
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16.5 DC Characteristics: PIC12F609/615/617 - E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended Conditions Device Characteristics Power-down Base Current (IPD)(2) PIC12F609/615/617 Min -- -- -- -- -- -- D022E D023E -- -- -- -- -- D024E -- -- -- D025E* -- -- -- D026E -- -- -- D027E -- -- Typ 0.05 0.15 0.35 0.5 2.5 9.5 5.0 6.0 50 55 60 30 45 75 39 59 98 5.5 7.0 8.5 0.2 0.36 Max 4.0 5.0 8.5 5.0 8.0 19 15 19 70 75 80 40 60 105 50 80 130 16 18 22 6.5 10 Units VDD A A A A A A A A A A A A A A A A A A A A A A 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 A/D Current(1), no conversion in progress T1OSC Current(1), 32.768 kHz CVREF Current(1) (low range) CVREF Current(1) (high range) Comparator Current(1), single comparator enabled BOR Current(1) WDT Current(1) Note WDT, BOR, Comparator, VREF and T1OSC disabled DC CHARACTERISTICS Param No. D020E
D021E
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
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PIC12F609/615/617/12HV609/615
16.6 DC Characteristics: PIC12HV609/615 - I (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Conditions Device Characteristics Power-down Base Current (IPD)(2,3) PIC12HV609/615 D021 Min -- -- -- -- -- -- D022 D023 -- -- -- -- -- D024 -- -- -- D025* -- -- -- D026 -- -- -- D027 -- -- Typ 135 210 260 135 210 265 215 265 185 265 320 165 255 330 175 275 355 140 220 270 210 260 Max 200 280 350 200 285 360 285 360 270 350 430 235 330 430 245 350 450 205 290 360 280 350 Units VDD A A A A A A A A A A A A A A A A A A A A A A 2.0 3.0 4.5 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 2.0 3.0 4.5 2.0 3.0 4.5 2.0 3.0 4.5 3.0 4.5 A/D Current(1), no conversion in progress T1OSC Current(1), 32.768 kHz CVREF Current(1) (low range) CVREF Current(1) (high range) Comparator Current(1), single comparator enabled BOR Current(1) WDT Current(1) Note WDT, BOR, Comparator, VREF and T1OSC disabled DC CHARACTERISTICS Param No. D020
* These parameters are characterized but not tested. Data in "Typ" column is at 4.5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. 3: Shunt regulator is always on and always draws operating current.
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16.7
DC Characteristics: PIC12HV609/615-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended Conditions Device Characteristics Power-down Base Current (IPD)(2,3) PIC12HV609/615 Min -- -- -- -- -- -- D022E D023E -- -- -- -- -- D024E -- -- -- D025E* -- -- -- D026E -- -- -- D027E -- -- Typ 135 210 260 135 210 265 215 265 185 265 320 165 255 330 175 275 355 140 220 270 210 260 Max 200 280 350 200 285 360 285 360 280 360 430 235 330 430 245 350 450 205 290 360 280 350 Units VDD A A A A A A A A A A A A A A A A A A A A A A 2.0 3.0 4.5 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 2.0 3.0 4.5 2.0 3.0 4.5 2.0 3.0 4.5 3.0 4.5 A/D Current(1), no conversion in progress T1OSC Current(1), 32.768 kHz CVREF Current(1) (low range) CVREF Current(1) (high range) Comparator Current(1), single comparator enabled BOR Current(1) WDT Current(1) Note WDT, BOR, Comparator, VREF and T1OSC disabled
DC CHARACTERISTICS Param No. D020E
D021E
* These parameters are characterized but not tested. Data in "Typ" column is at 4.5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. 3: Shunt regulator is always on and always draws operating current.
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16.8 DC Characteristics: PIC12F609/615/617/12HV609/615-I (Industrial) PIC12F609/615/617/12HV609/615-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Input Low Voltage I/O port: D030 D030A D031 D032 D033 D033A VIH D040 D040A D041 D042 D043 D043A D043B IIL D060 D061 D063 D070* IPUR VOL D080 VOH D090 * Note 1: 2: 3: 4: 5: 6: with Schmitt Trigger buffer MCLR OSC1 (XT and LP modes) OSC1 (HS mode) OSC1 (RC mode) Input Leakage Current(2,3) I/O ports GP3/MCLR(3,4) OSC1 GPIO Weak Pull-up Current(5) Output Low Voltage I/O ports Output High Voltage I/O ports(2) -- -- -- 50 -- -- VDD - 0.7 VDD - 0.7 0.1 0.7 0.1 250 -- -- -- -- 1 5 5 400 0.6 0.6 -- -- A A A A V V V V VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD, XT, HS and LP oscillator configuration VDD = 5.0V, VPIN = VSS IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOH = -2.5mA, VDD = 4.5V, -40C to +125C IOH = -3.0 mA, VDD = 4.5V, -40C to +85C with Schmitt Trigger buffer MCLR, OSC1 (RC mode) OSC1 (XT and LP modes) OSC1 (HS mode) Input High Voltage I/O ports: with TTL buffer 2.0 0.25 VDD + 0.8 0.8 VDD 0.8 VDD 1.6 0.7 VDD 0.9 VDD -- -- -- -- -- -- -- -- VDD VDD VDD VDD VDD VDD VDD V V V V V V V (NOTE 1) 4.5V VDD 5.5V 2.0V VDD 4.5V 2.0V VDD 5.5V with TTL buffer Vss Vss Vss VSS VSS VSS -- -- -- -- -- -- 0.8 0.15 VDD 0.2 VDD 0.2 VDD 0.3 0.3 VDD V V V V V V 4.5V VDD 5.5V 2.0V VDD 4.5V 2.0V VDD 5.5V (NOTE 1) Min Typ Max Units Conditions
DC CHARACTERISTICS Param No.
Sym VIL
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. This specification applies to GP3/MCLR configured as GP3 with the internal weak pull-up disabled. This specification applies to all weak pull-up pins, including the weak pull-up found on GP3/MCLR. When GP3/MCLR is configured as MCLR reset pin, the weak pull-up is always enabled. Applies to PIC12F617 only.
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16.8 DC Characteristics: PIC12F609/615/617/12HV609/615-I (Industrial) PIC12F609/615/617/12HV609/615-E (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Capacitive Loading Specs on Output Pins OSC2 pin All I/O pins Program Flash Memory D130 D130A D131 D132 D132A D133 D134 EP ED VPR VPEW VPEW TPEW TRETD * Note 1: 2: 3: 4: 5: 6: Cell Endurance Cell Endurance VDD for Read VDD for Bulk Erase/Write VDD for Row Erase/Write(6) Erase/Write cycle time Characteristic Retention 10K 1K VMIN 4.5 VMIN -- 40 100K 10K -- -- -- 2 -- -- -- 5.5 5.5 5.5 2.5 -- E/W E/W V V V ms Year Provided no other specifications are violated -40C TA +85C +85C TA +125C VMIN = Minimum operating voltage Min Typ Max Units Conditions
DC CHARACTERISTICS Param No. D101*
Sym
COSC2
--
--
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1
D101A* CIO
--
--
50
pF
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. This specification applies to GP3/MCLR configured as GP3 with the internal weak pull-up disabled. This specification applies to all weak pull-up pins, including the weak pull-up found on GP3/MCLR. When GP3/MCLR is configured as MCLR reset pin, the weak pull-up is always enabled. Applies to PIC12F617 only.
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16.9 Thermal Considerations
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. TH01 JA Sym Characteristic Thermal Resistance Junction to Ambient Typ 84.6* 149.5* 211* 60* 44* 41.2* 39.9* 39* 9* 3.0* 150* -- -- -- -- Units C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C W W W W Conditions 8-pin PDIP package 8-pin SOIC package 8-pin MSOP package 8-pin DFN 3x3mm package 8-pin DFN 4x4mm package 8-pin PDIP package 8-pin SOIC package 8-pin MSOP package 8-pin DFN 3x3mm package 8-pin DFN 4x4mm package PD = PINTERNAL + PI/O PINTERNAL = IDD x VDD (NOTE 1) PI/O = (IOL * VOL) + (IOH * (VDD VOH)) PDER = PDMAX (TDIE - TA)/JA (NOTE 2)
TH02
JC
Thermal Resistance Junction to Case
TH03 TH04 TH05 TH06 TH07 * Note 1: 2:
TDIE Die Temperature PD Power Dissipation PINTERNAL Internal Power Dissipation PI/O PDER I/O Power Dissipation Derated Power
These parameters are characterized but not tested. IDD is current to run the chip alone without driving any load on the output pins. TA = Ambient temperature.
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16.10 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O Port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low
T
Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z
Period Rise Valid High-impedance
FIGURE 16-3:
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Legend: CL=50 pF for all pins 15 pF for OSC2 output
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16.11 AC Characteristics: PIC12F609/615/617/12HV609/615 (Industrial, Extended)
FIGURE 16-4: CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1/CLKIN OS02 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OS04
OSC2/CLKOUT (CLKOUT Mode)
TABLE 16-1:
CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. OS01 Sym FOSC Characteristic External CLKIN Frequency(1) Min DC DC DC DC Oscillator Frequency
(1)
Typ -- -- -- -- 32.768 -- -- -- -- -- -- -- 30.5 -- -- -- TCY -- -- -- -- -- --
Max 37 4 20 20 -- 4 20 4 -- 10,000 1,000 -- DC -- -- --
Units kHz MHz MHz MHz kHz MHz MHz MHz s ns ns ns s ns ns ns ns s ns ns ns ns ns
Conditions LP Oscillator mode XT Oscillator mode HS Oscillator mode EC Oscillator mode LP Oscillator mode XT Oscillator mode HS Oscillator mode RC Oscillator mode LP Oscillator mode XT Oscillator mode HS Oscillator mode EC Oscillator mode LP Oscillator mode XT Oscillator mode HS Oscillator mode RC Oscillator mode TCY = 4/FOSC LP oscillator XT oscillator HS oscillator LP oscillator XT oscillator HS oscillator
-- 0.1 1 DC
OS02
TOSC
External CLKIN Period(1)
27 250 50 50
Oscillator Period(1)
-- 250 50 250
OS03 OS04*
TCY TOSH, TOSL TOSR, TOSF *
Instruction Cycle Time(1) External CLKIN High, External CLKIN Low External CLKIN Rise, External CLKIN Fall
200 2 100 20 0 0 0
OS05*
Note 1:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices.
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PIC12F609/615/617/12HV609/615
TABLE 16-2: OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. OS06 OS07 Sym TWARM INTOSC Characteristic Internal Oscillator Switch when running(3) Internal Calibrated INTOSC Frequency(2) (4MHz) Freq. Tolerance -- 1% 2% 5% Min -- 3.96 3.92 3.80 Typ -- 4.0 4.0 4.0 Max 2 4.04 4.08 4.2 Units TOSC MHz MHz MHz Conditions Slowest clock VDD = 3.5V, TA = 25C 2.5V VDD 5.5V, 0C TA +85C 2.0V VDD 5.5V, -40C TA +85C (Ind.), -40C TA +125C (Ext.) VDD = 3.5V, TA = 25C 2.5V VDD 5.5V, 0C TA +85C 2.0V VDD 5.5V, -40C TA +85C (Ind.), -40C TA +125C (Ext.) VDD = 2.0V, -40C to +85C VDD = 3.0V, -40C to +85C VDD = 5.0V, -40C to +85C
OS08
INTOSC
Internal Calibrated INTOSC Frequency(2) (8MHz)
1% 2% 5%
7.92 7.84 7.60
8.0 8.0 8.0
8.08 8.16 8.40
MHz MHz MHz
OS10*
TIOSC ST INTOSC Oscillator Wakeup from Sleep Start-up Time *
-- -- --
5.5 3.5 3
12 7 6
24 14 11
s s s
Note 1:
2: 3:
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. By design.
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FIGURE 16-5:
Cycle
CLKOUT AND I/O TIMING
Write Q4 Fetch Q1 Read Q2 Execute Q3
FOSC OS11 CLKOUT OS19 OS13 I/O pin (Input) OS15 I/O pin (Output) Old Value OS18, OS19 OS14 New Value OS17 OS20 OS21 OS16 OS18 OS12
TABLE 16-3:
CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. OS11 OS12 OS13 OS14 OS15 OS16 OS17 OS18 OS19 OS20* OS21* * Note 1: 2: Sym TOSH2CKL TOSH2CKH TCKL2IOV TIOV2CKH TOSH2IOV TOSH2IOI TIOV2OSH TIOR TIOF TINP TRAP Characteristic FOSC to CLKOUT (1) FOSC to CLKOUT
(1)
Min -- -- -- TOSC + 200 ns -- 50 20 -- -- -- -- 25 TCY
Typ -- -- -- -- 50 -- -- 15 40 28 15 -- --
Max 70 72 20 -- 70* -- -- 72 32 55 30 -- --
Units ns ns ns ns ns ns ns ns ns ns ns
Conditions VDD = 5.0V VDD = 5.0V
CLKOUT to Port out valid(1) Port input valid before CLKOUT(1) FOSC (Q1 cycle) to Port out valid FOSC (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to FOSC(Q2 cycle) (I/O in setup time) Port output rise time(2) Port output fall time(2) INT pin input high or low time GPIO interrupt-on-change new input level time
VDD = 5.0V VDD = 5.0V
VDD = 2.0V VDD = 5.0V VDD = 2.0V VDD = 5.0V
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. Includes OSC2 in CLKOUT mode.
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FIGURE 16-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Start-Up Time 32 30
Internal Reset(1) Watchdog Timer Reset(1) 34 I/O pins
Note 1: Asserted low.
31 34
FIGURE 16-7:
VDD
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VBOR
VBOR + VHYST
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset (due to BOR) *
33*
64 ms delay only if PWRTE bit in the Configuration Word register is programmed to `0'.
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TABLE 16-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 30 31* 32 33* 34* Sym TMCL TWDT TOST TPWRT TIOZ Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period(1, 2) Power-up Timer Period I/O High-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Voltage Brown-out Reset Hysteresis Brown-out Reset Minimum Detection Period Min 2 5 10 10 -- 40 -- Typ -- -- 20 20 1024 65 -- Max -- -- 30 35 -- 140 2.0 Units s s ms ms Conditions VDD = 5V, -40C to +85C VDD = 5V, -40C to +125C VDD = 5V, -40C to +85C VDD = 5V, -40C to +125C
TOSC (NOTE 3) ms s
35 36* 37*
VBOR VHYST TBOR
2.0 -- 100
2.15 100 --
2.3 -- --
V mV s
(NOTE 4) VDD VBOR
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: By design. 3: Period of the slower clock. 4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended.
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FIGURE 16-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI 40 41
42
T1CKI 45 47 46 49
TMR0 or TMR1
TABLE 16-5:
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 40* 41* 42* Sym TT0H TT0L TT0P Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 Greater of: 20 or TCY + 40 N 0.5 TCY + 20 15 30 0.5 TCY + 20 15 30 Greater of: 30 or TCY + 40 N 60 -- 2 TOSC Typ -- -- -- -- -- Max -- -- -- -- -- Units ns ns ns ns ns N = prescale value (2, 4, ..., 256) Conditions
45*
TT1H
T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler Asynchronous T1CKI Low Time Synchronous, No Prescaler Synchronous, with Prescaler Asynchronous
-- -- -- -- -- -- --
-- -- -- -- -- -- --
ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8)
46*
TT1L
47*
TT1P
T1CKI Input Synchronous Period Asynchronous
-- 32.768 --
-- -- 7 TOSC
ns kHz -- Timers in Sync mode
48 49*
FT1
Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN)
TCKEZTMR1 Delay from External Clock Edge to Timer Increment *
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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PIC12F609/615/617/12HV609/615
FIGURE 16-9: PIC12F615/617/HV615 CAPTURE/COMPARE/PWM TIMINGS (ECCP)
CCP1 (Capture mode)
CC01 CC03 Note: Refer to Figure 16-3 for load conditions.
CC02
TABLE 16-6:
PIC12F615/617/HV615 CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP)
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. CC01* CC02* CC03* Sym TccL TccH TccP Characteristic CCP1 Input Low Time CCP1 Input High Time CCP1 Input Period No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5TCY + 20 20 0.5TCY + 20 20 3TCY + 40 N Typ -- -- -- -- -- Max -- -- -- -- -- Units ns ns ns ns ns N = prescale value (1, 4 or 16) Conditions
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
TABLE 16-7:
COMPARATOR SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. CM01 CM02 Sym VOS VCM Characteristics Input Offset Voltage(2) Input Common Mode Voltage Common Mode Rejection Ratio Response Time(1) Falling Rising CM05* TMC2COV Comparator Mode Change to Output Valid CM06* VHYS Input Hysteresis Voltage Min -- 0 +55 -- -- -- -- Typ 5.0 -- -- 150 200 -- 45 Max 10 VDD - 1.5 -- 600 1000 10 60 Units mV V dB ns ns s mV Comments
CM03* CMRR CM04* TRT
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Response time is measured with one comparator input at (VDD - 1.5)/2 - 100 mV to (VDD - 1.5)/2 + 20 mV. The other input is at (VDD -1.5)/2. 2: Input offset voltage is measured with one comparator input at (VDD - 1.5V)/2.
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TABLE 16-8: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. CV01* CV02* CV03* CV04* Sym CLSB CACC CR CST Characteristics Step Size(2) Absolute Accuracy(3) Unit Resistor Value (R) Settling Time(1) Min -- -- -- -- -- -- Typ VDD/24 VDD/32 -- -- 2k -- Max -- -- 1/2 1/2 -- 10 Units V V LSb LSb s Comments Low Range (VRR = 1) High Range (VRR = 0) Low Range (VRR = 1) High Range (VRR = 0)
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from `0000' to `1111'. 2: See Section 9.10 "Comparator Voltage Reference" for more information. 3: Absolute Accuracy when CVREF output is (VDD -1.5).
TABLE 16-9:
VOLTAGE REFERENCE SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Min 0.5 1.05 -- Typ 0.6 1.20 10 Max 0.7 1.35 -- Units V V s Comments
VR Voltage Reference Specifications Param No. VR01 VR02 VR03* * Symbol VP6OUT V1P2OUT TSTABLE Characteristics VP6 voltage output V1P2 voltage output Settling Time
These parameters are characterized but not tested.
TABLE 16-10: SHUNT REGULATOR SPECIFICATIONS (PIC12HV609/615 only)
SHUNT REGULATOR CHARACTERISTICS Param No. SR01 SR02 SR03* SR04 SR05 * Symbol Characteristics Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Min 4.75 4 -- 0.01 -- Typ 5 -- -- -- 180 Max 5.4 50 150 10 -- Units V mA ns F A To 1% of final value Bypass capacitor on VDD pin Includes band gap reference current Comments
VSHUNT Shunt Voltage ISHUNT CLOAD ISNT Shunt Current Load Capacitance Regulator operating current TSETTLE Settling Time
These parameters are characterized but not tested.
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TABLE 16-11: PIC12F615/617/HV615 A/D CONVERTER (ADC) CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param Sym No. AD01 AD02 AD03 AD04 AD07 NR EIL EDL EOFF EGN Characteristic Resolution Integral Error Differential Error Offset Error Gain Error Reference Voltage
(3)
Min -- -- -- -- -- 2.2 2.5 VSS --
Typ -- -- -- +1.5 -- --
Max 10 bits 1 1 +2.0 1 -- VDD VREF 10
Units bit
Conditions
LSb VREF = 5.12V(5) LSb No missing codes to 10 bits VREF = 5.12V(5) LSb VREF = 5.12V(5) LSb VREF = 5.12V(5) V Absolute minimum to ensure 1 LSb accuracy V k
AD06 VREF AD06A AD07 AD08 VAIN ZAIN
Full-Scale Range Recommended Impedance of Analog Voltage Source VREF Input Current(3)
-- --
AD09* IREF
10 --
-- --
1000 50
A A
During VAIN acquisition. Based on differential of VHOLD to VAIN. During A/D conversion cycle.
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: ADC VREF is from external VREF or VDD pin, whichever is selected as reference input. 4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. 5: VREF = 5V for PIC12HV615.
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PIC12F609/615/617/12HV609/615
TABLE 16-12: PIC12F615/617/HV615 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. Sym Characteristic A/D Clock Period A/D Internal RC Oscillator Period AD131 TCNV Conversion Time (not including Acquisition Time)(1) Min 1.6 3.0 3.0 1.6 -- Typ -- -- 6.0 4.0 11 Max Units 9.0 9.0 9.0 6.0 -- s s s s TAD Conditions TOSC-based, VREF 3.0V TOSC-based, VREF full range(3) ADCS<1:0> = 11 (ADRC mode) At VDD = 2.5V At VDD = 5.0V Set GO/DONE bit to new data in A/D Result register
AD130* TAD
AD132* TACQ Acquisition Time AD133* TAMP Amplifier Settling Time AD134 TGO Q4 to A/D Clock Start -- -- --
11.5 -- TOSC/2 TOSC/2 + TCY
-- 5 -- --
s s -- -- If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle. 2: See Section 10.3 "A/D Acquisition Requirements" for minimum conditions. 3: Full range for PIC12HV609/HV615 powered by the shunt regulator is the 5V regulated voltage.
FIGURE 16-10:
PIC12F615/617/HV615 A/D CONVERSION TIMING (NORMAL MODE)
1 TCY AD131 AD130
BSF ADCON0, GO AD134 Q4 A/D CLK A/D Data ADRES ADIF GO Sample Note 1: AD132
(TOSC/2(1))
9
8 OLD_DATA
7
6
3
2
1
0 NEW_DATA 1 TCY DONE
Sampling Stopped
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
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PIC12F609/615/617/12HV609/615
FIGURE 16-11: PIC12F615/617/HV615 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO AD134 Q4 A/D CLK A/D Data ADRES ADIF GO Sample AD132 Sampling Stopped 9 8 7 6 3 2 1 0 NEW_DATA 1 TCY DONE (TOSC/2 + TCY(1)) 1 TCY AD131 AD130
OLD_DATA
Note 1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
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2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
16.12 High Temperature Operation
This section outlines the specifications for the PIC12F615 device operating in a temperature range between -40C and 150C.(4) The specifications between -40C and 150C(4) are identical to those shown in DS41288 and DS80329. Note 1: Writes are not allowed for Program Memory above 125C. Flash
2: All AC timing specifications are increased by 30%. This derating factor will include parameters such as TPWRT. 3: The temperature range indicator in the part number is "H" for -40C to 150C.(4) Example: PIC12F615T-H/ST indicates the device is shipped in a TAPE and reel configuration, in the MSOP package, and is rated for operation from -40C to 150C.(4) 4: AEC-Q100 reliability testing for devices intended to operate at 150C is 1,000 hours. Any design in which the total operating time from 125C to 150C will be greater than 1,000 hours is not warranted without prior written approval from Microchip Technology Inc.
TABLE 16-13: ABSOLUTE MAXIMUM RATINGS
Parameter Max. Current: VDD Max. Current: VSS Max. Current: PIN Max. Current: PIN Pin Current: at VOH Pin Current: at VOL Port Current: GPIO Port Current: GPIO Maximum Junction Temperature Note: Source/Sink Source Sink Source Sink Source Sink Source Sink Value 20 50 5 10 3 8.5 20 50 155 Units mA mA mA mA mA mA mA mA C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.
2010 Microchip Technology Inc.
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PIC12F609/615/617/12HV609/615
TABLE 16-14: DC CHARACTERISTICS FOR IDD SPECIFICATIONS FOR PIC12F615-H (High Temp.)
Param No. D010 Supply Current (IDD) D011 A D012 A Device Characteristics Condition Units Min -- -- -- -- -- -- A mA D013 A D014 A mA D016 A D017 A mA D018 A D019 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- mA -- -- Typ 13 19 32 135 185 300 240 360 0.660 75 155 345 185 325 0.665 245 360 620 395 0.620 1.20 175 285 530 2.20 2.80 Max VDD 58 67 92 316 400 537 495 680 1.20 158 338 792 357 625 1.30 476 672 1.10 757 1.20 2.20 332 518 972 4.10 4.80 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 4.5 5.0 IDD HS OSC (20 MHz) IDD EXTRC (4 MHz) IDD INTOSC (8 MHz) IDD INTOSC (4 MHz) IDD EC OSC (4 MHz) IDD EC OSC (1 MHz) IDD XT OSC (4 MHz) IDD XT OSC (1 MHz) IDD LP OSC (32 kHz) Note
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TABLE 16-15: DC CHARACTERISTICS FOR IPD SPECIFICATIONS FOR PIC12F615-H (High Temp.)
Param No. D020E Device Characteristics Power Down Base Current Condition Units Min -- A -- -- D021E A D022E D023E A A -- -- -- A -- -- -- -- -- -- -- -- D024E A D025E A D026E A D027E -- -- -- -- -- -- -- -- -- A -- -- Typ 0.05 0.15 0.35 0.5 2.5 9.5 5.0 6.0 105 110 116 50 55 60 30 45 75 39 59 98 5.5 7.0 8.5 0.2 0.3 Max VDD 12 13 14 20 25 36 28 36 195 210 220 105 110 125 58 85 142 76 114 190 30 35 45 12 15 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 IPD (A2D on, not converting) IPD (T1 OSC, 32 kHz) IPD (CVREF, Low Range) IPD (CVREF, High Range) IPD Current (One Comparator Enabled) IPD Current (Both Comparators Enabled) BOR Current WDT Current IPD Base Note
TABLE 16-16: WATCHDOG TIMER SPECIFICATIONS FOR PIC12F615-H (High Temp.)
Param No. 31 Sym TWDT Characteristic Watchdog Timer Time-out Period (No Prescaler) Units ms Min 6 Typ 20 Max 70 Conditions 150C Temperature
TABLE 16-17: LEAKAGE CURRENT SPECIFICATIONS FOR PIC12F615-H (High Temp.)
Param No. D061 D062 Note 1: 2: Sym IIL IIL Characteristic Input Leakage Current(1) (GP3/RA3/MCLR) Input Leakage Current(2) (GP3/RA3/MCLR) Units A A Min -- 50 Typ 0.5 250 Max 5.0 400 Conditions VSS VPIN VDD VDD = 5.0V
This specification applies when GP3/RA3/MCLR is configured as an input with the pull-up disabled. The leakage current for the GP3/RA3/MCLR pin is higher than for the standard I/O port pins. This specification applies when GP3/RA3/MCLR is configured as the MCLR reset pin function with the weak pull-up enabled.
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PIC12F609/615/617/12HV609/615
TABLE 16-18: OSCILLATOR PARAMETERS FOR PIC12F615-H (High Temp.)
Param No. OS08 Note 1: Sym Characteristic Frequency Tolerance 10% Units MHz Min 7.2 Typ 8.0 Max 8.8 Conditions 2.0V VDD 5.5V -40C TA 150C
INTOSC Int. Calibrated INTOSC Freq.(1)
To ensure these oscillator frequency tolerances, Vdd and Vss must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended.
TABLE 16-19: COMPARATOR SPECIFICATIONS FOR PIC12F615-H (High Temp.)
Param No. CM01 Sym VOS Characteristic Input Offset Voltage Units mV Min -- Typ 5 Max 20 Conditions (VDD - 1.5)/2
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17.0
Note:
DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
"Typical" represents the mean of the distribution at 25C. "Maximum" or "minimum" represents (mean + 3) or (mean 3) respectively, where s is a standard deviation, over each temperature range.
FIGURE 17-1:
60
PIC12F609/615/617 IDD LP (32 kHz) vs. VDD
50
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
Maximum
40
IDD LP (A)
Typical
30
20
10
0 1 2 3 4 5 6
VDD (V)
FIGURE 17-2:
600
PIC12F609/615/617 IDD EC (1 MHz) vs. VDD
Maximum Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Typical
500
IDD EC (A)
400 300 200 100 0 1
2
3
4
5
6
VDD (V)
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PIC12F609/615/617/12HV609/615
FIGURE 17-3:
1200
PIC12F609/615/617 IDD EC (4 MHz) vs. VDD
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Maximum
1000
800
IDD EC (A)
Typical
600
400
200
0 1 2 3
VDD (V)
4
5
6
FIGURE 17-4:
1200
PIC12F609/615/617 IDD XT (1 MHz) vs. VDD
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
1000
800
IDD XT (A)
600
Maximum
400
Typical
200
0 1 2 3
VDD (V)
4
5
6
FIGURE 17-5:
1200 1000 800
PIC12F609/615/617 IDD XT (4 MHz) vs. VDD
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Maximum
IDD XT (A)
Typical
600 400 200 0 1 2 3 4 5 6
VDD (V)
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PIC12F609/615/617/12HV609/615
FIGURE 17-6:
900 800 700
PIC12F609/615/617 IDD INTOSC (4 MHz) vs. VDD
Maximum Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
Typical
IDD INTOSC (A)
600 500 400 300 200 100 0 1 2 3
VDD (V)
4
5
6
FIGURE 17-7:
1800 1600 1400
PIC12F609/615/617 IDD INTOSC (8 MHz) vs. VDD
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Maximum
Typical
IDD INTOSC (A)
1200 1000 800 600 400 200 0 1 2 3 4
VDD (V)
5
6
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PIC12F609/615/617/12HV609/615
FIGURE 17-8:
800
PIC12F609/615617 IDD EXTRC (4 MHz) vs. VDD
Maximum Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Typical
700 600
IDD EXTRC (A)
500 400 300 200 100 0 1 2 3 4
VDD (V)
5
6
FIGURE 17-9:
PIC12F609/615/617 IDD HS (20 MHz) vs. VDD
4
Maximum
3
Typical Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) IDD HS (mA)
2
1
0 4 5 6
VDD (V)
DS41302D-page 174
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-10:
9
PIC12F609/615/617 IPD BASE vs. VDD
Typical: Statistical Mean @25C Extended
8
7
Industrial: Mean (Worst-Case Temp) + 3 (-40C to 85C) Extended: Mean (Worst-Case Temp) + 3 (-40C to 125C)
6
IPD BASE (A)
5
4
3
2
Industrial
1
Typical
0 1 2 3
VDD (V)
4
5
6
FIGURE 17-11:
90
PIC12F609/615/617 IPD COMPARATOR (SINGLE ON) vs. VDD
Extended
80
Industrial
70
IPD CMP (A)
Typical
60
50
Typical: Statistical Mean @25C
40
Industrial: Mean (Worst-Case Temp) + 3 (-40C to 85C) Extended: Mean (Worst-Case Temp) + 3 (-40C to 125C)
30 1 2 3 4 5 6
VDD (V)
2010 Microchip Technology Inc.
DS41302D-page 175
PIC12F609/615/617/12HV609/615
FIGURE 17-12:
20 18 16
PIC12F609/615/617 IPD WDT vs. VDD
Extended Typical: Statistical Mean @25C Industrial: Mean (Worst-Case Temp) + 3 (-40C to 85C) Extended: Mean (Worst-Case Temp) + 3 (-40C to 125C) Typical Industrial
IPD WDT (A)
14 12 10 8 6 4 2 0 1
2
3
4
5
6
VDD (V)
FIGURE 17-13:
20
PIC12F609/615/617 IPD BOR vs. VDD
Typical: Statistical Mean @25C
Extended
18
Industrial: Mean (Worst-Case Temp) + 3 (-40C to 85C) Extended: Mean (Worst-Case Temp) + 3 (-40C to 125C)
16
14
IPD BOR (A)
Industrial
12
10
8
Typical
6
4
2
0 1 2 3 4 5 6
VDD (V)
DS41302D-page 176
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-14:
140 Typical: Statistical Mean @25C 120 Industrial: Mean (Worst-Case Temp) + 3 (-40C to 85C) Extended: Mean (Worst-Case Temp) + 3 (-40C to 125C)
PIC12F609/615/617 IPD CVREF (LOW RANGE) vs. VDD
Maximum
Typical
100
80
IPD CVREF (A)
60
40
20
0 1 2 3 4 5 6
VDD (V)
FIGURE 17-15:
120
PIC12F609/615/617 IPD CVREF (HI RANGE) vs. VDD
Typical: Statistical Mean @25C
Maximum
100 80 60 40 20 0 1
Industrial: Mean (Worst-Case Temp) + 3 (-40C to 85C) Extended: Mean (Worst-Case Temp) + 3 (-40C to 125C)
IPD CVREF (A)
Typical
2
3 VDD (V)
4
5
6
2010 Microchip Technology Inc.
DS41302D-page 177
PIC12F609/615/617/12HV609/615
FIGURE 17-16:
25
PIC12F609/615/617 IPD T1OSC vs. VDD
Typical: Statistical Mean @25C Industrial: Mean (Worst-Case Temp) + 3 (-40C to 85C) Extended: Mean (Worst-Case Temp) + 3 (-40C to 125C) Extended
20
IPD T1OSC (A)
15
Industrial
10
Typical
5
0 1 2 3 4 5 6
VDD (V)
FIGURE 17-17:
14
PIC12F615/617 IPD A/D vs. VDD
Typical: Statistical Mean @25C Extended
12
10
Industrial: Mean (Worst-Case Temp) + 3 (-40C to 85C) Extended: Mean (Worst-Case Temp) + 3 (-40C to 125C)
IPD A2D (A)
8
6
4
Industrial
2
Typical
0 1 2 3 4 5 6
VDD (V)
DS41302D-page 178
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-18:
450 400 350 300
PIC12HV609/615 IDD LP (32 kHz) vs. VDD
Maximum Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Typical
IDD LP (A)
250 200 150 100 50 0 1 2 3 4 5
VDD (V)
FIGURE 17-19:
1000 900 800
PIC12HV609/615 IDD EC (1 MHz) vs. VDD
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
Maximum
IDD EC (A)
700 600
Typical
500 400 300 200 100 1 2 3 4 5
VDD (V)
FIGURE 17-20:
1400 1200
PIC12HV609/615 IDD EC (4 MHz) vs. VDD
Maximum
IDD EC (A)
1000 800 600 400 200 0 1
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
Typical
2
3
4
5
VDD (V)
2010 Microchip Technology Inc.
DS41302D-page 179
PIC12F609/615/617/12HV609/615
FIGURE 17-21:
900 800 700
PIC12HV609/615 IDD XT (1 MHz) vs. VDD
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
Maximum
IDD XT (A)
600 500 400 300 200 100 0 1 2 3 4
Typical
5
VDD (V)
FIGURE 17-22:
1400 1200 1000
PIC12HV609/615 IDD XT (4 MHz) vs. VDD
Maximum
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
Typical
IDD XT (A)
800 600 400 200 0 1 2 3 4 5
VDD (V)
FIGURE 17-23:
1200 1000
PIC12HV609/615 IDD INTOSC (4 MHz) vs. VDD
Maximum Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Typical
IDD INTOSC (A)
800 600 400 200 0 1
2
3
4
5
VDD (V)
DS41302D-page 180
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-24:
2000
PIC12HV609/615 IDD INTOSC (8 MHz) vs. VDD
Maximum
IDD INTOSC (A)
1500
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
Typical
1000
500
0 1 2 3 4 5
VDD (V)
FIGURE 17-25:
1200 1000
PIC12HV609/615 IDD EXTRC (4 MHz) vs. VDD
Maximum
IDD EXTRC (A)
800 600 400 200
0
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
Typical
1
2
3
4
5
VDD (V)
FIGURE 17-26:
400 350
PIC12HV609/615 IPD BASE vs. VDD
Maximum
IPD BASE (A)
300 250 200 150 100 50 0 1
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
Typical
2
3
4
5
VDD (V)
2010 Microchip Technology Inc.
DS41302D-page 181
PIC12F609/615/617/12HV609/615
FIGURE 17-27:
500
PIC12HV609/615 IPD COMPARATOR (SINGLE ON) vs. VDD
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
Maximum
400
IPD CMP (A)
Typical
300
200
100 0 1 2 3 4 5
VDD (V)
FIGURE 17-28:
400 350
PIC12HV609/615 IPD WDT vs. VDD
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Maximum
IPD WDT (A)
300
Typical
250 200 150 100 50 0 1 2 3 4 5
VDD (V)
FIGURE 17-29:
400
PIC12HV609/615 IPD BOR vs. VDD
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Maximum
350
IPD BOR (A)
300
Typical
250
200
150
100 2
3
4
5
VDD (V)
DS41302D-page 182
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-30:
500
PIC12HV609/615 IPD CVREF (LOW RANGE) vs. VDD
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Maximum Typical
IPD CVREF (A)
400 300 200
100
0 1 2 3 4 5
VDD (V)
FIGURE 17-31:
500
PIC12HV609/615 IPD CVREF (HI RANGE) vs. VDD
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Maximum
400
IPD CVREF (A)
Typical
300
200
100
0 1 2 3 4 5
VDD (V)
FIGURE 17-32:
400 350 300
PIC12HV609/615 IPD T1OSC vs. VDD
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
Maximum
IPD T1OSC (A)
Typical
250 200 150 100 50
0
1 2 3 4 5
VDD (V)
2010 Microchip Technology Inc.
DS41302D-page 183
PIC12F609/615/617/12HV609/615
FIGURE 17-33:
400 350 300
PIC12HV615 IPD A/D vs. VDD
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
Maximum
IPD A2D (A)
Typical
250 200 150 100 50
0 2 3 4 5
VDD (V)
FIGURE 17-34:
0.8
VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)
0.7
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
Max. 125C
0.6
0.5 VOL (V)
Max. 85C
0.4 Typical 25C 0.3
0.2 Min. -40C 0.1
0.0 5.0 5.5 6.0 6.5 7.0 7.5 IOL (mA) 8.0 8.5 9.0 9.5 10.0
DS41302D-page 184
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-35:
0.45 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)
0.40
Max. 125C Max. 85C
0.35
0.30
VOL (V)
0.25 Typ. 25C 0.20 Min. -40C
0.15
0.10
0.05
0.00 5.0 5.5 6.0 6.5 7.0 7.5 IOL (mA) 8.0 8.5 9.0 9.5 10.0
FIGURE 17-36:
3.5
VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)
3.0 Max. -40C Typ. 25C
2.5
Min. 125C 2.0 VOH (V) 1.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) 1.0 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 IOH (mA) -2.5 -3.0 -3.5 -4.0 2010 Microchip Technology Inc.
DS41302D-page 185
PIC12F609/615/617/12HV609/615
FIGURE 17-37:
5.5
VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V)
5.0 Max. -40C
Typ. 25C 4.5 VOH (V) Min. 125C
4.0
3.5
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 IOH (mA) -3.0 -3.5 -4.0 -4.5 -5.0
FIGURE 17-38:
1.7
TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
1.5
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Max. -40C
1.3 VIN (V) Typ. 25C 1.1 Min. 125C 0.9
0.7
0.5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
DS41302D-page 186
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-39:
4.0 VIH Max. 125C 3.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
VIH Min. -40C
3.0
VIN (V)
2.5
2.0 VIL Max. -40C 1.5 VIL Min. 125C
1.0
0.5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 17-40:
16
TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
14 85C 12 25C 10 Time (s) -40C 8
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
6
4
2
0 2.0
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
2010 Microchip Technology Inc.
DS41302D-page 187
PIC12F609/615/617/12HV609/615
FIGURE 17-41:
25
MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
20
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
Time (s)
15 85C 25C 10 -40C
5
0 2.0
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
FIGURE 17-42:
10 9 8 7
MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) 85C
Time (s)
6 25C 5 -40C 4 3 2 1 0 2.0
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
DS41302D-page 188
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-43:
5 4 3 Change from Calibration (%) 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25C)
FIGURE 17-44:
5 4 3 Change from Calibration (%) 2 1 0 -1 -2 -3 -4 -5 2.0
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (85C)
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
2010 Microchip Technology Inc.
DS41302D-page 189
PIC12F609/615/617/12HV609/615
FIGURE 17-45:
5 4 3 Change from Calibration (%) 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125C)
FIGURE 17-46:
5 4 3 Change from Calibration (%) 2 1 0 -1 -2 -3 -4 -5 2.0
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40C)
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
DS41302D-page 190
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-47:
0.61 2.5V 0.6 Reference Voltage (V) 3V 4V 5V 5.5V
0.6V REFERENCE VOLTAGE vs. TEMP (TYPICAL)
0.59
0.58
0.57
0.56 -60 -40 -20 0 20 40 Temp (C) 60 80 100 120 140
FIGURE 17-48:
1.26 Reference Voltage (V) 1.25 1.24 1.23 1.22 1.21 1.2 -60
1.2V REFERENCE VOLTAGE vs. TEMP (TYPICAL)
2.5V 3V 4V 5V 5.5V
-40
-20
0
20
40
60
80
100
120
140
Temp (C)
FIGURE 17-49:
5.16 5.14 Shunt Regulator Voltage (V) 5.12 5.1 5.08 5.06 5.04 5.02 5 4.98 4.96 0
SHUNT REGULATOR VOLTAGE vs. INPUT CURRENT (TYPICAL)
-40C 25C 85C 125C
10
20
30 Input Current (mA)
40
50
60
2010 Microchip Technology Inc.
DS41302D-page 191
PIC12F609/615/617/12HV609/615
FIGURE 17-50:
5.16 Shunt Regulator Voltage (V) 5.14 5.12 5.1 5.08 5.06 5.04 5.02 5 4.98 4.96 -60 -40 -20 0 20 40 Temp (C) 60 80 100 120 20 mA 15 mA 10 mA 4 mA 140 50 mA 40 mA
SHUNT REGULATOR VOLTAGE vs. TEMP (TYPICAL)
FIGURE 17-51:
1000 900 800 Response Time (nS) 700 600 500 400 300 200 100 0
COMPARATOR RESPONSE TIME (RISING EDGE)
Max. 125C
Note: VCM = (VDD - 1.5V)/2 V+ input = VCM V- input = Transition from VCM + 100mV to VCM - 20mV
Max. 85C
Typ. 25C Min. -40C
2.0
2.5 VDD (V)
4.0
5.5
DS41302D-page 192
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-52:
1000 900 800 700 Response Time (nS) 600 500 400 300 200 100 0 2.0 2.5 VDD (V) 4.0 5.5 Typ. 25C Min. -40C Note: VCM = (VDD - 1.5V)/2 V+ input = VCM V- input = Transition from VCM - 100mV to VCM + 20MV Max. 125C
COMPARATOR RESPONSE TIME (FALLING EDGE)
Max. 85C
FIGURE 17-53:
55 50 45 40 35 Time (ms) 30
WDT TIME-OUT PERIOD vs. VDD OVER TEMPERATURE
125C 25 20 25C 15 -40C 10 5 1.5 2 2.5 3 VDD (V) 3.5 4 4.5 5 5.5 6 85C
2010 Microchip Technology Inc.
DS41302D-page 193
PIC12F609/615/617/12HV609/615
NOTES:
DS41302D-page 194
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
18.0
18.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP (.300") Example
XXXXXXXX XXXXXNNN YYWW
8-Lead SOIC (.150") XXXXXXXX XXXXYYWW NNN 8-Lead MSOP
XXFXXX/P 017 e3 0610
Example PICXXCXX /SN0610 e3 017 Example
XXXXXX YWWNNN
602/MS 610017
8-Lead DFN (3x3 mm)
Example
XXXX YYWW NNN
8-Lead DFN (4x4 mm) (for PIC12F609/615/HV609/615 devices only)
XXXX 0610 017
Example
XXXXXX XXXXXX YYWW NNN
Legend: XX...X Y YY WW NNN
XXXXXX XXXX e3 0610 017
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( can be found on the outer packaging for this package.
e3
*
)
e3
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
*
Standard PIC device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
2010 Microchip Technology Inc.
DS41302D-page 195
PIC12F609/615/617/12HV609/615
18.2 Package Details
The following sections give the technical details of the packages.
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PIC12F609/615/617/12HV609/615
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2010 Microchip Technology Inc.
DS41302D-page 197
PIC12F609/615/617/12HV609/615
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DS41302D-page 198
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
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APPENDIX A:
Revision A
This is a new data sheet.
DATA SHEET REVISION HISTORY
APPENDIX B:
MIGRATING FROM OTHER PIC(R) DEVICES
This discusses some of the issues in migrating from other PIC devices to the PIC12F6XX Family of devices.
Revision B (05/2008)
Added Graphs. Revised 28-Pin ICD Pinout, Electrical Specifications Section, Package Details.
B.1
PIC12F675 to PIC12F609/615/ 12HV609/615
FEATURE COMPARISON
PIC12F675 20 MHz 1024 64 10-bit 1/1 8 Y RA0/1/2/4/5 PIC12F609/ 615/ 12HV609/615 20 MHz 1024 64 10-bit (615 only) 2/1 (615) 1/1 (609) 8 Y GP0/1/2/4/5, MCLR 1 Y (615) 4/8 MHz Y (PIC12HV609/ 615)
TABLE B-1:
Feature
Revision C (09/2009)
Updated adding the PIC12F617 device throughout the entire data sheet; Added Figure 2-2 to Memory Organization section; Added section 3 "FLASH PROGRAM MEMORY SELF READ/SELF WRITE CONTROL (FOR PIC12F617 ONLY)"; Updated Register 12-1; Updated Table12-5 adding PMCON1, PMCON2, PMADRL, PMADRH, PMDATL, PMDATH; Added section 16-12 in the Electrical Specification section; Other minor edits.
Max Operating Speed Max Program Memory (Words) SRAM (bytes) A/D Resolution Timers (8/16-bit)
Revision D (01/2010)
Updated Figure 17-50; Revised 16.8 Characteristics; Removed Preliminary Status. DC
Oscillator Modes Brown-out Reset Internal Pull-ups Interrupt-on-change Comparator ECCP INTOSC Frequencies Internal Shunt Regulator
RA0/1/2/3/4/5 GP0/1/2/3/4/5 1 N 4 MHz N
Note:
This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device.
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NOTES:
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INDEX
A
A/D Specifications.................................................... 164, 165 Absolute Maximum Ratings .............................................. 143 AC Characteristics Industrial and Extended ............................................ 156 Load Conditions ........................................................ 155 ADC Acquisition Requirements ........................................... 86 Associated registers.................................................... 88 Block Diagram............................................................. 79 Calculating Acquisition Time....................................... 86 Channel Selection....................................................... 80 Configuration............................................................... 80 Configuring Interrupt ................................................... 83 Conversion Clock........................................................ 80 Conversion Procedure ................................................ 83 Internal Sampling Switch (RSS) Impedance................ 86 Interrupts..................................................................... 81 Operation .................................................................... 82 Operation During Sleep .............................................. 82 Port Configuration ....................................................... 80 Reference Voltage (VREF)........................................... 80 Result Formatting........................................................ 82 Source Impedance...................................................... 86 Special Event Trigger.................................................. 82 Starting an A/D Conversion ........................................ 82 ADC (PIC12F615/617/HV615 Only) ................................... 79 ADCON0 Register............................................................... 84 ADRESH Register (ADFM = 0) ........................................... 85 ADRESH Register (ADFM = 1) ........................................... 85 ADRESL Register (ADFM = 0)............................................ 85 ADRESL Register (ADFM = 1)............................................ 85 Analog Input Connection Considerations............................ 68 Analog-to-Digital Converter. See ADC ANSEL Register (PIC12F609/HV609) ................................ 45 ANSEL Register (PIC12F615/617/HV615) ......................... 45 APFCON Register............................................................... 24 Assembler MPASM Assembler................................................... 140 PIC12F609/12HV609 ................................................... 7 PIC12F615/617/12HV615 ............................................ 8 PWM (Enhanced) ....................................................... 97 Resonator Operation .................................................. 39 Timer1 .................................................................. 57, 58 Timer2 ........................................................................ 65 TMR0/WDT Prescaler ................................................ 53 Watchdog Timer ....................................................... 122 Brown-out Reset (BOR).................................................... 112 Associated Registers................................................ 113 Specifications ........................................................... 160 Timing and Characteristics ....................................... 159
C
C Compilers MPLAB C18.............................................................. 140 MPLAB C30.............................................................. 140 Calibration Bits.................................................................. 109 Capture Module. See Enhanced Capture/Compare/ PWM (ECCP) Capture/Compare/PWM (CCP) Associated registers w/ Capture................................. 91 Associated registers w/ Compare............................... 93 Associated registers w/ PWM................................... 105 Capture Mode............................................................. 90 CCP1 Pin Configuration ............................................. 90 Compare Mode........................................................... 92 CCP1 Pin Configuration ..................................... 92 Software Interrupt Mode ............................... 90, 92 Special Event Trigger ......................................... 92 Timer1 Mode Selection................................. 90, 92 Prescaler .................................................................... 90 PWM Mode................................................................. 94 Duty Cycle .......................................................... 95 Effects of Reset .................................................. 96 Example PWM Frequencies and Resolutions, 20 MHZ .................................. 95 Example PWM Frequencies and Resolutions, 8 MHz .................................... 95 Operation in Sleep Mode.................................... 96 Setup for Operation ............................................ 96 System Clock Frequency Changes .................... 96 PWM Period ............................................................... 95 Setup for PWM Operation .......................................... 96 CCP1CON (Enhanced) Register ........................................ 89 Clock Sources External Modes........................................................... 38 EC ...................................................................... 38 HS ...................................................................... 39 LP ....................................................................... 39 OST .................................................................... 38 RC ...................................................................... 40 XT ....................................................................... 39 Internal Modes............................................................ 40 INTOSC .............................................................. 40 INTOSCIO .......................................................... 40 CMCON0 Register.............................................................. 72 CMCON1 Register.............................................................. 73 Code Examples A/D Conversion .......................................................... 83 Assigning Prescaler to Timer0.................................... 54 Assigning Prescaler to WDT....................................... 54 Changing Between Capture Prescalers ..................... 90 Indirect Addressing..................................................... 25
B
Block Diagrams (CCP) Capture Mode Operation ................................. 90 ADC ............................................................................ 79 ADC Transfer Function ............................................... 87 Analog Input Model ............................................... 68, 87 Auto-Shutdown ......................................................... 101 CCP PWM................................................................... 94 Clock Source............................................................... 37 Comparator ................................................................. 67 Compare ..................................................................... 92 Crystal Operation ........................................................ 39 External RC Mode....................................................... 40 GP0 and GP1 Pins...................................................... 47 GP2 Pins..................................................................... 48 GP3 Pin....................................................................... 49 GP4 Pin....................................................................... 50 GP5 Pin....................................................................... 51 In-Circuit Serial Programming Connections.............. 125 Interrupt Logic ........................................................... 119 MCLR Circuit............................................................. 111 On-Chip Reset Circuit ............................................... 110
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Initializing GPIO .......................................................... 43 Saving Status and W Registers in RAM ................... 121 Writing to Flash Program Memory .............................. 34 Code Protection ................................................................ 124 Comparator ......................................................................... 67 Associated registers.................................................... 78 Control ........................................................................ 69 Gating Timer1 ............................................................. 73 Operation During Sleep .............................................. 71 Overview ..................................................................... 67 Response Time ........................................................... 69 Synchronizing COUT w/Timer1 .................................. 73 Comparator Hysteresis ....................................................... 77 Comparator Voltage Reference (CVREF) ............................ 74 Effects of a Reset........................................................ 71 Comparator Voltage Reference (CVREF) Response Time ........................................................... 69 Comparator Voltage Reference (CVREF) Specifications ............................................................ 163 Comparators C2OUT as T1 Gate ..................................................... 60 Effects of a Reset........................................................ 71 Specifications ............................................................ 162 Compare Module. See Enhanced Capture/Compare/ PWM (ECCP) (PIC12F615/617/HV615 only) CONFIG Register.............................................................. 108 Configuration Bits.............................................................. 107 CPU Features ................................................................... 107 Customer Change Notification Service ............................. 209 Customer Notification Service........................................... 209 Customer Support ............................................................. 209 Timer Resources ........................................................ 89 Enhanced Capture/Compare/PWM (PIC12F615/617/HV615 Only).................................... 89 Errata .................................................................................... 6
F
Firmware Instructions ....................................................... 129 Flash Program Memory Self Read/Self Write Control (For PIC12F617 only)..................................... 27 Fuses. See Configuration Bits
G
General Purpose Register File ........................................... 12 GPIO................................................................................... 43 Additional Pin Functions ............................................. 44 ANSEL Register ................................................. 44 Interrupt-on-Change ........................................... 44 Weak Pull-Ups.................................................... 44 Associated registers ................................................... 52 GP0 ............................................................................ 47 GP1 ............................................................................ 47 GP2 ............................................................................ 48 GP3 ............................................................................ 49 GP4 ............................................................................ 50 GP5 ............................................................................ 51 Pin Descriptions and Diagrams .................................. 47 Specifications ........................................................... 158 GPIO Register .................................................................... 43
H
High Temperature Operation ............................................ 167
D
Data EEPROM Memory Associated Registers .................................................. 35 Data Memory....................................................................... 11 DC and AC Characteristics Graphs and Tables ................................................... 171 DC Characteristics Extended and Industrial ............................................ 152 Industrial and Extended ............................................ 145 Development Support ....................................................... 139 Device Overview ................................................................... 7
I
ID Locations...................................................................... 124 In-Circuit Debugger........................................................... 125 In-Circuit Serial Programming (ICSP)............................... 125 Indirect Addressing, INDF and FSR registers..................... 25 Instruction Format............................................................. 129 Instruction Set................................................................... 129 ADDLW..................................................................... 131 ADDWF..................................................................... 131 ANDLW..................................................................... 131 ANDWF..................................................................... 131 MOVF ....................................................................... 134 BCF .......................................................................... 131 BSF........................................................................... 131 BTFSC ...................................................................... 131 BTFSS ...................................................................... 132 CALL......................................................................... 132 CLRF ........................................................................ 132 CLRW ....................................................................... 132 CLRWDT .................................................................. 132 COMF ....................................................................... 132 DECF ........................................................................ 132 DECFSZ ................................................................... 133 GOTO ....................................................................... 133 INCF ......................................................................... 133 INCFSZ..................................................................... 133 IORLW ...................................................................... 133 IORWF...................................................................... 133 MOVLW .................................................................... 134 MOVWF .................................................................... 134 NOP .......................................................................... 134 RETFIE ..................................................................... 135 RETLW ..................................................................... 135 RETURN................................................................... 135
E
ECCP. See Enhanced Capture/Compare/PWM ECCPAS Register ............................................................. 102 EEDAT Register.................................................................. 28 EEDATH Register ............................................................... 28 Effects of Reset PWM mode ................................................................. 96 Electrical Specifications .................................................... 143 Enhanced Capture/Compare/PWM (ECCP) Enhanced PWM Mode ................................................ 97 Auto-Restart...................................................... 103 Auto-shutdown .................................................. 101 Half-Bridge Application ....................................... 99 Half-Bridge Application Examples..................... 104 Half-Bridge Mode ................................................ 99 Output Relationships (Active-High and Active-Low) ................................................. 98 Output Relationships Diagram ............................ 98 Programmable Dead Band Delay ..................... 104 Shoot-through Current ...................................... 104 Start-up Considerations .................................... 100 Specifications ............................................................ 162
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RLF ........................................................................... 136 RRF........................................................................... 136 SLEEP ...................................................................... 136 SUBLW ..................................................................... 136 SUBWF ..................................................................... 137 SWAPF ..................................................................... 137 XORLW..................................................................... 137 XORWF..................................................................... 137 Summary Table......................................................... 130 INTCON Register ................................................................ 20 Internal Oscillator Block INTOSC Specifications............................................ 157, 158 Internal Sampling Switch (RSS) Impedance ........................ 86 Internet Address................................................................ 209 Interrupts ........................................................................... 118 ADC ............................................................................ 83 Associated Registers ................................................ 120 Context Saving.......................................................... 121 GP2/INT .................................................................... 118 GPIO Interrupt-on-Change........................................ 119 Interrupt-on-Change.................................................... 44 Timer0....................................................................... 119 TMR1 .......................................................................... 60 INTOSC Specifications ............................................. 157, 158 IOC Register ....................................................................... 46 Oscillator Parameters ....................................................... 157 Oscillator Specifications.................................................... 156 Oscillator Start-up Timer (OST) Specifications ........................................................... 160 OSCTUNE Register............................................................ 41
P
P1A/P1B/P1C/P1D.See Enhanced Capture/Compare/ PWM (ECCP) ............................................................. 97 Packaging ......................................................................... 195 Marking..................................................................... 195 PDIP Details ............................................................. 196 PCL and PCLATH............................................................... 25 Stack........................................................................... 25 PCON Register ........................................................... 23, 113 PICSTART Plus Development Programmer..................... 142 PIE1 Register ..................................................................... 21 Pin Diagram PIC12F609/HV609 (PDIP, SOIC, MSOP, DFN)........... 4 PIC12F615/617/HV615 (PDIP, SOIC, MSOP, DFN) .... 5 Pinout Descriptions PIC12F609/12HV609 ................................................... 9 PIC12F615/617/12HV615 .......................................... 10 PIR1 Register ..................................................................... 22 PMADRH and PMADRL Registers ..................................... 27 PMCON1 and PMCON2 Registers..................................... 27 Power-Down Mode (Sleep)............................................... 123 Power-on Reset (POR)..................................................... 111 Power-up Timer (PWRT) .................................................. 111 Specifications ........................................................... 160 Precision Internal Oscillator Parameters .......................... 158 Prescaler Shared WDT/Timer0................................................... 54 Switching Prescaler Assignment ................................ 54 Program Memory ................................................................ 11 Map and Stack............................................................ 11 Programming, Device Instructions.................................... 129 Protection Against Spurious Write ...................................... 32 PWM Mode. See Enhanced Capture/Compare/PWM ........ 97 PWM1CON Register......................................................... 105
L
Load Conditions ................................................................ 155
M
MCLR ................................................................................ 111 Internal ...................................................................... 111 Memory Organization.......................................................... 11 Data ............................................................................ 11 Program ...................................................................... 11 Microchip Internet Web Site .............................................. 209 Migrating from other PICmicro Devices ............................ 203 MPLAB ASM30 Assembler, Linker, Librarian ................... 140 MPLAB ICD 2 In-Circuit Debugger ................................... 141 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator .................................................... 141 MPLAB Integrated Development Environment Software .. 139 MPLAB PM3 Device Programmer .................................... 141 MPLAB REAL ICE In-Circuit Emulator System................. 141 MPLINK Object Linker/MPLIB Object Librarian ................ 140
R
Reader Response............................................................. 210 Reading the Flash Program Memory.................................. 30 Read-Modify-Write Operations ......................................... 129 Registers ADCON0 (ADC Control 0) .......................................... 84 ADRESH (ADC Result High) with ADFM = 0) ............ 85 ADRESH (ADC Result High) with ADFM = 1) ............ 85 ADRESL (ADC Result Low) with ADFM = 0).............. 85 ADRESL (ADC Result Low) with ADFM = 1).............. 85 ANSEL (Analog Select) .............................................. 45 APFCON (Alternate Pin Function Register) ............... 24 CCP1CON (Enhanced CCP1 Control) ....................... 89 CMCON0 (Comparator Control 0) .............................. 72 CMCON1 (Comparator Control 1) .............................. 73 CONFIG (Configuration Word) ................................. 108 Data Memory Map (PIC12F609/HV609) .................... 12 Data Memory Map (PIC12F615/617/HV615) ............. 13 ECCPAS (Enhanced CCP Auto-shutdown Control) . 102 EEDAT (EEPROM Data) ............................................ 28 EEDATH (EEPROM Data) ......................................... 28 GPIO........................................................................... 43 INTCON (Interrupt Control) ........................................ 20 IOC (Interrupt-on-Change GPIO) ............................... 46 OPTION_REG (OPTION)........................................... 19
O
OPCODE Field Descriptions ............................................. 129 Operation During Code Protect........................................... 32 Operation During Write Protect ........................................... 32 Operational Amplifier (OPA) Module AC Specifications...................................................... 163 OPTION Register ................................................................ 19 OPTION_REG Register ...................................................... 55 Oscillator Associated registers.............................................. 41, 63 Oscillator Module .......................................................... 27, 37 EC ............................................................................... 37 HS ............................................................................... 37 INTOSC ...................................................................... 37 INTOSCIO................................................................... 37 LP................................................................................ 37 RC............................................................................... 37 RCIO ........................................................................... 37 XT ............................................................................... 37
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OPTION_REG (Option) .............................................. 55 OSCTUNE (Oscillator Tuning) .................................... 41 PCON (Power Control Register) ................................. 23 PCON (Power Control) ............................................. 113 PIE1 (Peripheral Interrupt Enable 1) ........................... 21 PIR1 (Peripheral Interrupt Register 1) ........................ 22 PWM1CON (Enhanced PWM Control) ..................... 105 Reset Values (PIC12F609/HV609) ........................... 115 Reset Values (PIC12F615/617/HV615) .................... 116 Reset Values (special registers) ............................... 117 Special Function Registers ......................................... 12 Special Register Summary (PIC12F609/HV609) .. 14, 16 Special Register Summary (PIC12F615/617/HV615) .............................. 15, 17 STATUS ...................................................................... 18 T1CON ........................................................................ 62 T2CON ........................................................................ 66 TRISIO (Tri-State GPIO) ............................................. 44 VRCON (Voltage Reference Control) ......................... 76 WPU (Weak Pull-Up GPIO) ........................................ 46 Reset................................................................................. 110 Revision History ................................................................ 203 Timer2 (PIC12F615/617/HV615 Only) Associated registers ................................................... 66 Timers Timer1 T1CON ............................................................... 62 Timer2 T2CON ............................................................... 66 Timing Diagrams A/D Conversion......................................................... 165 A/D Conversion (Sleep Mode) .................................. 166 Brown-out Reset (BOR)............................................ 159 Brown-out Reset Situations ...................................... 112 CLKOUT and I/O ...................................................... 158 Clock Timing ............................................................. 156 Comparator Output ..................................................... 67 Enhanced Capture/Compare/PWM (ECCP)............. 162 Half-Bridge PWM Output .................................... 99, 104 INT Pin Interrupt ....................................................... 120 PWM Auto-shutdown Auto-restart Enabled......................................... 103 Firmware Restart .............................................. 103 PWM Output (Active-High) ......................................... 98 PWM Output (Active-Low) .......................................... 98 Reset, WDT, OST and Power-up Timer ................... 159 Time-out Sequence Case 1 .............................................................. 114 Case 2 .............................................................. 114 Case 3 .............................................................. 114 Timer0 and Timer1 External Clock ........................... 161 Timer1 Incrementing Edge ......................................... 61 Wake-up from Interrupt............................................. 124 Timing Parameter Symbology .......................................... 155 TRISIO ................................................................................ 43 TRISIO Register ................................................................. 44
S
Shoot-through Current ...................................................... 104 Sleep Power-Down Mode ................................................... 123 Wake-up.................................................................... 123 Wake-up using Interrupts .......................................... 123 Software Simulator (MPLAB SIM)..................................... 140 Special Event Trigger.......................................................... 82 Special Function Registers ................................................. 12 STATUS Register................................................................ 18
T
T1CON Register.................................................................. 62 T2CON Register.................................................................. 66 Thermal Considerations .................................................... 154 Time-out Sequence........................................................... 113 Timer0 ................................................................................. 53 Associated Registers .................................................. 55 External Clock ............................................................. 54 Interrupt....................................................................... 55 Operation .............................................................. 53, 57 Specifications ............................................................ 161 T0CKI .......................................................................... 54 Timer1 ................................................................................. 57 Associated registers.................................................... 63 Asynchronous Counter Mode ..................................... 59 Reading and Writing ........................................... 59 Comparator Synchronization ...................................... 61 ECCP Special Event Trigger (PIC12F615/617/HV615 Only) ............................ 61 ECCP Time Base (PIC12F615/617/HV615 Only) ....... 60 Interrupt....................................................................... 60 Modes of Operation .................................................... 57 Operation During Sleep .............................................. 60 Oscillator ..................................................................... 59 Prescaler ..................................................................... 59 Specifications ............................................................ 161 Timer1 Gate Inverting Gate ..................................................... 60 Selecting Source........................................... 60, 73 Synchronizing COUT w/Timer1 .......................... 73 TMR1H Register ......................................................... 57 TMR1L Register .......................................................... 57
V
Voltage Reference (VR) Specifications ........................................................... 163 Voltage Reference. See Comparator Voltage Reference (CVREF) Voltage References Associated registers ................................................... 78 VP6 Stabilization ........................................................ 74 VREF. SEE ADC Reference Voltage
W
Wake-up Using Interrupts ................................................. 123 Watchdog Timer (WDT).................................................... 121 Associated registers ................................................. 122 Specifications ........................................................... 160 WPU Register ..................................................................... 46 Writing the Flash Program Memory .................................... 32 WWW Address ................................................................. 209 WWW, On-Line Support ....................................................... 6
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THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
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Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
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READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
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PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) Device: PIC12F609, PIC12F609T(1), PIC12HV609, PIC12HV609T(1), PIC12F615, PIC12F615T(1), PIC12HV615, PIC12HV615T(1), PIC12F617, PIC12F617T(1) (High Temp)(3) (Industrial) (Extended) c) d) e) Temperature Range: H I E = -40C to +150C = -40C to +85C = -40C to +125C f) g) h) Package: P SN MS MF MD = = = = = Plastic DIP (PDIP) 8-lead Small Outline (150 mil) (SOIC) Micro Small Outline (MSOP) 8-lead Plastic Dual Flat, No Lead (3x3) (DFN) 8-lead Plastic Dual Flat, No Lead (4x4)(DFN)(1,2) i) PIC12F615-E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 PIC12F615-I/SN = Industrial Temp., SOIC package, 20 MHz PIC12F615T-E/MF = Tape and Reel, Extended Temp., 3x3 DFN, 20 MHz PIC12F609T-E/MF = Tape and Reel, Extended Temp., 3x3 DFN, 20 MHz PIC12HV615T-E/MF = Tape and Reel, Extended Temp., 3x3 DFN, 20 MHz PIC12HV609T-E/MF = Tape and Reel, Extended Temp., 3x3 DFN, 20 MHz PIC12F617T-E/MF = Tape and Reel, Extended Temp., 3x3 DFN, 20 MHz PIC12F617-I/P = Industrial Temp., PDIP package, 20 MHz PIC12F615-H/SN = High Temp., SOIC package, 20 MHz T = in tape and reel for MSOP, SOIC and DFN packages only. Not available for PIC12F617. High Temp. available for PIC12F615 only.
Note 1: 2: 3:
Pattern:
QTP, SQTP or ROM Code; Special Requirements (blank otherwise)
2010 Microchip Technology Inc.
DS41302D-page 211
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
01/05/10
DS41302D-page 212
2010 Microchip Technology Inc.

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